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Lecture 1 – Overview (rSp06)
Functional Verification of Hardware
Designs
- EE764 – Functional Verification of Hardware
Designs
- Course Topic Objectives
- Learn to use verification tools and experiment on actual circuits designed in industry (or equal to)
- Learn to plan & carry out effective functional verification of a design
- Learn to work in teams to debug designs
- Both code and debug HDL design code
Lecture 1 – Overview (rSp06)
Functional Verification of Hardware
Designs (cont)
- By the end of the course the student will have
- Verified several examples provided by the instructor (some may come from industry)
- Have an understanding of why verification is important
- Have an understanding of the level of complexity present in the verification of modern microcircuits
Lecture 1 – Overview (rSp06)
History 101
- VHDL 1st^ standardized in 1987 by IEEE
- VHDL about to be standardized again and will include many new aspects, several aimed specifically aimed toward verification (PSL)
- Verilog 1 st^ standardized in 1995 by IEEE
- Hardware Description Languages were the beginning of several new advances in chip and system design - Simulation of chips and systems - Synthesis of digital hardware - Verification
Lecture 1 – Overview (rSp06)
History continued
- 1990 focus – Does chip work at all?
- 2000 focus – Does chip work in the
system environment as specified?
- Today – more efficient verification than in
Lecture 1 – Overview (rSp06)
Today’s design issue
- Gate counts and system complexity growing
exponentially
- Bulk of time in design of an new IC is spent on
verification
- In most companies there is at least a 1-to-1 ratio of design engineers to verification engineers.
- Real problem is not how to create the 12 Billion (or
more) gate IC but how to verify it.
Lecture 1 – Overview (rSp06)
What is verification?
- Verification is not a testbench or a series of testbenches.
- Verification is a process used to demonstrate the functional correctness of a design. It is the act of ensuring that the logic design conforms to the specifications.
- Verification does not insure that the specification is correct. (Next real advance in design will likely be specification languages!)
Lecture 1 – Overview (rSp06)
Verification testbenches
- In verification the testbench provides the inputs and monitors the outputs.
- The challenge of verification is to determine what input patterns to supply and what is the expected output of a properly working design
Lecture 1 – Overview (rSp06)
EE762 testbenches
- The testbenches used in EE762 check the essentials
of basic correct operation and are less than a typical verification testbench. The goal of the EE testbenches is to catch typical mistakes, check the operation in central and corner cases, and provide feedback to the student (the error signal).
- They are somewhat less than a testbench to be used
for production of an IC.
Lecture 1 – Overview (rSp06)
Verification Testplan
- Schedule
- Required tools
- Input and completion criteria
- Specific tests
- What is expected to be found with each test
- What’s not covered by the tests
Lecture 1 – Overview (rSp06)
Other parts of cycle
- RIT – stands for Release Interface Tape
- RIT is sending the design to the chip fab.
- Chip is fabricated and then IC is tested.
- Escape Analysis – Fully understand any bugs in
fabricated part.
- A critical part of the IC verification process
- Reproduce in simulation if possible
- Lack of ability to reproduce means fix cannot be verified
- Could misunderstand the bug
