VHDL Design using Structural Modeling and Component Instantiation, Slides of Digital Systems Design

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Lecture 13

VHDL Structural Modeling

Outline

• Structural VHDL

• Use of hierarchy

• Component instantiation statements

• Concurrent statements

• Test Benches

• READING: Dewey 12.1, 12.2, 12.3, 12.4, 13.1,

Structural Descriptions

• A structural description of a system is expressed in terms

of subsystems interconnected by signals

• Each subsystem may be another design (component) or a

process

• Component instantiation and port maps

entity entity_name (architecture_identifier)

port map (

port_name => signal_name

expression

open,

Example of Component Instantiation

entity DRAM_controller is

port (rd, wr, mem: in bit;

ras, cas, we, ready: out bit);

end entity DRAM_controller;

• We can then perform a component instantiation as follows

assuming that there is a corresponding architecture called

“fpld” for the entity.

main_mem_cont : entity work.DRAM_controller(fpld)

port map (rd=>cpu_rd, wr=>cpu_wr,

mem=>cpu_mem, ready=> cpu_rdy,

ras=>mem_ras, cas=>mem_cas, we=>mem_we);

Behavioral Description of Register

Architecture behavior of reg4 is

begin

storage : process is

variable stored_d0, stored_d1, stored_d2, stored_d3: bit;

begin

if en = „1‟ and clk = „1‟ then

stored_d0 := d0; -- variable assignment

stored_d1 := d1;

stored_d2 := d2;

stored_d3 := d3;

endif;

q0 <= stored_d0 after 5 nsec;

q1 <= stored_d1 after 5 nsec;

q2 <= stored_d2 after 5 nsec;

q3 <= stored_d3 after 5 nsec;

wait on d0, d1, d2, d3;

end process storage;

end architecture behavior;

Structural Composition of Register

q

d_latch q

d

clk

d_latch q

d

clk

d_latch q

d

clk

d_latch q

d

clk

and y

a

b

d

d

d

d

en

clk

q

q

q

int_clk

Structural VHDL Description of Register

entity reg4 is

port(d0, d1, d2, d3, en, clk: in bit;

q0, q1, q2, q3: out bit);

end entity reg4;

architecture struct of reg4 is

signal int_clk : bit;

begin

bit0: entity work.d_latch(basic) port map(d0, int_clk, q0); bit1: entity work.d_latch(basic) port map(d1, int_clk, q1); bit2: entity work.d_latch(basic)

port map(d2, int_clk, q2); bit0: entity work.d_latch(basic) port map(d3, int_clk, q3); gate: entity work.and2(basic) port map(en, clk, int_clk);

end architecture struct;

Mixed Structural and Behavioral Models

• Models need not be purely structural or behavioral

• Often it is useful to specify a model with some

parts composed of interconnected component

instances and other parts using processes

• Use signals as a way to join component instances

and processes

• A signal can be associated with a port of a

component instance and can be assigned to or read

in a process

Component and Signal Declarations

• The declarative part of the architecture STRUCTURE

contains:

– component declaration

– signal declaration

• Example of component declaration

– component AND2_OP

– port (A, B: in bit; Z : out bit);

– end component;

• Components and design entities are associated by signals,

e.g. A_IN, B_IN

• Signals are needed to interconnect components

– signal INT1, INT2, INT3: bit;

Component Instantiation Statements

• The statement part of an architecture body of a structural

VHDL description contains component instantiation

statements

• FORMAT

label : component_name port map (positional association of ports);

label : component_name port map (named association of ports);

• EXAMPLES

A1: AND2_OP port map (A_IN, B_IN, INT1);

A2: AND2_OP port map (A=>A_IN, C=>C_IN,Z=>INT2);

Concurrent Signal Assignments

entity XOR2_OP is

port (A, B: in BIT; Z : out BIT);

end entity;

-- body

architecture AND_OR of XOR2_OP is

begin

Z <= (not A and B) or (A and not B);

end AND_OR;

• The signal assignment Z <= .. Implies that the statement is

executed whenever an associated signal changes value

Concurrent Signal Assignment

entity XOR2_OP is

port (A, B: in BIT; Z : out BIT);

end entity;

-- body

architecture AND_OR_CONCURRENT of XOR2_OP is

--signal declaration;

signal INT1, INT2 : BIT;

begin -- different order, same effect

INT1 <= A and not B; -- INT1 <= A and not B;

INT2 <= not A and B; -- Z <= INT1 or INT2;

Z <= INT1 or INT2; -- INT2 <= not A and B;

end AND_OR_CONCURRENT;

• Above, the first two statements will be executed

when A or B changes, and third if Z changes

• Order of statements in the text does not matter

Data Flow Modeling of Combinational

Logic

• Consider a parity function of 8 inputs

entity EVEN_PARITY is

port (BVEC : in BIT_VECTOR(7 downto 0);

PARITY: out BIT);

end EVEN_PARITY;

architecture DATA_FLOW of EVEN_PARITY is

begin

PARITY <= BVEC(0) xor BVEC(1) xor BVEC(2) xor BVEC(3) xor

BVEC(4) xor BVEC(5) xor BVEC(6) xor BVEC(7)

end DATA_FLOW;

Alternative Logic Implementations of

PARITY

TREE CONFIGURATION

CASCADE CONFIGURATION