Computer Architecture Exam Questions and Solutions: C952, Exams of Computer Science

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Computer

Architecture C

Exam Questions and

Complete Solutions

Denning [Date] [Course title]

What access does a register file operate under to properly function? - Answer: read and write access what is the binary representation of instructions? - Answer: machine language Which feature of the IBM 360/91 was incorporated into the majority of microprocessors developed in the 21st century? - Answer: Algorithm innovations allowed the improved parallel execution of instructions. Which key design element changed in 2005 to drive continued improvements in computing capability? - Answer: Multiprocessor architecture Which term refers to the same instruction applied to multiple data streams? - Answer: SIMD What makes vector code better than conventional code? - Answer: the frequency of pipeline hazards is lower Which two elements are required to implement R format arithmetic logic unit operations? - Answer: ALU and register file Which component of a computer moderates the actions of other components? - Answer: control Overflow occurs when: - Answer: -you add two integer values with the same left most bit and end up with a different left most bit -when you subtract a value with a different leading bit than the other value, and the result is the first value's sign What is the approximate range of an unsigned 64 bit integer? - Answer: 0 to 18,446,744,073,709,551, DRAM - Answer: memory built as an integrated circuit with 50 nanosecond access times SRAM - Answer: faster than dram and less dense than dram, it is an integrated circuit

What is superscalar as it relates to parallelization? - Answer: A technique that enables the processor to execute more than one instruction per clock cycle by selecting them during execution The value of b is stored in r1, c is stored in r2, and a is stored in r0. Which set of ARM instructions will accomplish a = b & c? - Answer: AND r0, r1, r Registers X1, X2, X3 have corresponding data stored in each location: X1: A X2: B X3: C Which set of ARM instructions will accomplish A=B+C? - Answer: ADD X1, X2, X The variables f and g are assigned to the registers X3 and X4, respectively in these ARM instructions. Loop: SUBS XZR, X3, X B.GE Exit LSL X3, X3, 1 B Loop Exit: What are the corresponding statements in the C language? - Answer: while (f < g) { f = f << 1; } Given this set of ARM instructions, where b is at offset 0, e is at offset 8, and a is at offset 24: LDUR X1, [X0,#0]

LDUR X2, [X0,#8]

ADD X3, X1, X

STUR X3, [X0,#24]

What is the corresponding C language statement? - Answer: a = b + e; What is the number of bits used in virtual memory with ARMv8? - Answer: 48. 64 total bits, but 16 are unused. Which register will be populated with the reason for an exception in LEGv8 architecture? - Answer: the ESR, or Exception Syndrome Register Which statement about the operating system describes how virtual memory is allocated in ARM architecture? - Answer: It loads the page table register to refer to the page table of the process. What is used by virtual memory to increase performance? - Answer: Translation-lookaside buffer (looks for items used recently) What maps virtual memory to real memory by using page tables? - Answer: Each guest operating system manages virtual memory independently. What are two benefits of using virtual machines? - Answer: software and hardware abstraction Which type of processing is used if a program executes a process that takes turns waiting for user input?

• Answer: sequential Which factor in parallel processing is not bound by Amdahl's Law? - Answer: strong scaling What is an advantage of multiprocessor architecture? - Answer: It increases throughput.

How many seconds is the CPU performance for the task? - Answer: 7.5 seconds CPU time formula - Answer: = (Instructions) (CPI) (Clock Cycle Time) A cache has 16 one-word blocks. Memory blocks are mapped to fully associative caches. Memory block is 15. What is the cache position given the cache configuration and memory block? - Answer: Any of the 16 blocks, since it is fully associated. Where can it go in a direct mapped cache? - Answer: Only one spot. In a two way associative cache? - Answer: 2 blocks A program has a CPI of 10 on a target platform. The processor pipeline is expanded and clock rate is increased by a factor of 5, but the CPI fails to decrease accordingly. Which factor is negatively affecting performance? - Answer: cache memory Four processors (1, 2, 3, and 4) have clock frequencies of 200 Mhz, 300 Mhz, 500 Mhz, and 700 Mhz, respectively. Suppose: Processor 1 can execute an instruction with an average of 5 steps. Processor 2 can execute an instruction with an average of 3 steps. Processor 3 can execute an instruction with an average of 3 steps. Processor 4 can execute an instruction with an average of 5 steps. Which processor should be selected to improve performance for the execution of the same instruction?

• Answer: Processor 3. Find this by dividing instruction count by clock rate or instruction count multiplied by clock time.

CPU execution time for a program - Answer: execution time for a program = clock cycles x clock time Which technique should be implemented to reduce cache miss rate? - Answer: blocking Which set-associative cache will improve overall performance? - Answer: two way A program requires one billion instructions to execute on a processor running at 4 GHz. Exactly 50% of the instructions execute in three clock cycles, 30% execute in four clock cycles, and 20% execute in five clock cycles resulting in an execution time of 1.075 seconds. Which adjustment improves overall performance by 12%? - Answer: 70% execute at three cycles and 30% at four cycles Which instruction of the ARM architecture excludes a carry value after the arithmetic calculation? - Answer: reverse subtract Which three components or aspects specify the statement of a virtual machine? - Answer: page table, program counters, and registers A storage solution for video editing is being planned. The requirements are: Largest storage space No redundancy Fastest I/O speed Which RAID solution should be implemented? - Answer: RAID 0 Which computer architecture idea is analogous to the assembly line? - Answer: performance via pipelining

Which solution will meet these needs? - Answer: hypervisor A system designer wants to lower the cost of communicating at a high clock rate over the network. How can this goal be accomplished? - Answer: Reduce the distance of each link