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Exam questions for the bachelor of engineering in electronic engineering degree at cork institute of technology. The exam covers topics in ic design, delta-sigma modulators, vhdl coding, bcd/decimal decoders, rf electronics, and smith charts. Students are required to answer questions related to s-parameters, impedance matching, and signal flow graphs, among others.
Typology: Exams
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Instructions: There are two sections (A and B) Answer any five questions Please use separate answer books for each section. Each question carries equal marks (20) Maximum available mark is 100.
Examiners: Mr. P. Collins Dr. J. Barrett Prof. W.G. Hurley Dr. S. Foley
(a) Outline the construction of a double-poly capacitor. Show where parasitic capacitors arise in it’s construction. [5 marks]
(b) Draw the circuit diagram of a switched capacitor integrator and derive the sampled data transfer function. Ignore any parasitic capacitors in the circuit. [5 marks]
(c) Draw the circuit diagram of a switched capacitor integrator which is insensitive to parasitic capacitances found in a poly-poly capacitor. Derive the sampled data transfer function. Explain clearly how the effect of any parasitic capacitors are removed. [10 marks]
a) A signal of interest being sampled by an ADC has a bandwidth of fO but is sampled at a frequency fS ( where fS > 2fO) by the ADC. The ADC is followed by a brickwall digital low pass filter with passband fO. If OSR = fS /2fO show that the SNR of the system is : SNR = 6.02N + 1.76 + 10log 10 (OSR). [5 marks]
b) Explain how a 1st^ order delta-sigma modulator can be used to shape the quantization noise of a quantizer. Make reference to the noise transfer function and the signal transfer function in your explanation. [5 marks]
c) The magnitude of the Noise Transfer Function of a 1st^ order delta-sigma modulator is
f S
f NTF Sin π
3
fS is the sampling frequency of the ADC. fO is the frequency range of interest on the input. OSR = fS /2fO. ∆ is the LSB size.
The spectral density of the quantization noise is S
E f
[6 marks]
d) Using the equation for PE from part (c), show that the maximum SNR of a 1st^ order delta- sigma N-bit ADC = 6.02N + 1.76 - 5.17 + 30*log 10 (OSR) for a sine wave input signal. [4 marks]
a) A BCD/Decimal decoder is a circuit that has one 4-bit input port and 10 output ports. The value of the input port is used to set one of the output ports high. The truth table is shown in Fig Q4a. Write VHDL code for a behavioral model of the decoder. You should make use of a Case statement and logic vectors in your answer. [8 marks]
INPUTS OUTPUTS A3 A2 A1 A0 OP0 OP1 OP2 OP3 OP4 OP5 OP6 OP7 OP8 OP 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1
Fig Q4a.
b) A logic block has the following inputs : a clock signal, serial data line, polarity control line. It has one output, Q. The block is to look for an occurrence of the sequence ‘101’ in the input serial stream if the polarity control line is high, and for an occurrence of the sequence ‘010’ if the polarity control line is low. After an occurrence of the correct input pattern, the output is to go high for 3 clock cycles. The serial data input can be ignored during these 3 cycles. The block should then start monitoring the input again. Write VHDL code that uses a state machine to implement the logic block. [12 marks]
Question 5 Impedance matching and s-parameters
(a) Use the Smith Chart to find the input impedance at 903MHz of the circuit in Figure Q. (5 marks)
Figure Q.
(b) Use the Smith Chart to design a two element matching network between a source of 2+j1.5Ω and a load with a reflection coefficient of 0.4∠ 74 ° at 2.5GHz. The matching network should be high-pass. (5 marks)
(c) Outline three advantages of s-parameters compared to other types of network parameters (e.g. Z or Y) (2 marks)
(d) What are ABCD parameters and in what application are they particularly useful? (2 marks)
(e) What are signal flow graphs and what are they used for? (2 marks) (f) Draw the signal flow graph for a two port network (4 marks)
7.5nH
10pF 15nH 20nH
4.7pF 100 Ω
Q7. “Power Amplifiers”
(a) What is the origin of “intermodulation distortion”? (2 marks) (b) What is “two-tone intermodulation testing” and how is it carried out? (2 marks) (c) What is “adjacent channel power ratio”? (2 marks) (d) Figure Q.7 shows a DC bias circuit for an RF transistor “Q” stabilised with respect to the collector current through Q. Briefly outline how the circuit stabilises the current. (2 marks) (e) What are the purposes of components L1 and C2 in the circuit in Figure Q.7? (2 marks)
(f) An RF power transistor has an input impedance of 1.3-j0.9Ω and an output impedance of 2.6+j1.4Ω. ( These are the actual impedances seen looking in at the input and output ports ). Design two-element input and output matching networks to match this transistor to a 4+j3Ω source and a 50Ω load at 900MHz. DC is to be blocked at both input and output. (8 marks)
Figure Q.7. Circuit for Q7(d) and Q7(e)
Q8 Oscillators and mixers
(a) Briefly outline the basic operating principle of (i) The reflection (negative resistance) type oscillator (4 marks) (ii) The feedback (resonant circuit) type oscillator (4 marks) (b) The active device in a negative resistance oscillator has a negative resistance varying linearly with its current (I 0 ) as shown in Figure Q8. Assuming that device reactance is negligible, show that, for maximum oscillator power output, the diode should be presented with a load resistance of one third the start-up resistance of the active device i.e.: (8 marks) Figure Q
(c) Briefly define the following terms used in mixer design: (4 marks) (i) Up-converter (ii) High-side injection (iii) Conversion loss (iv) Compression
R (^) D(Io )
-R (^) m
Io(Max)
RD(Max)
R (^) L (^) RD(Io )
R (^) L =− RD (max) = Rm = RD
___input_name, __input_name : IN STD_LOGIC; __bidir_name, __bidir_name : INOUT STD_LOGIC; __output_name, _output_name : OUT STD_LOGIC); END COMPONENT;
----- Component instantiation.
___instance_name: __component_name PORT MAP (__component_port => __connect_port, __component_port => _connect_port);
----- Concurrent signal assignment statement.
___signal <= _expression;
------ Conditional signal assignment. ( concurrent if statement ).
___label: __signal <= __expression WHEN __boolean_expression ELSE __expression WHEN __boolean_expression ELSE _expression;
----- Constant declaration.
_CONSTANT __constant_name : __type_name := _constant_value;
----- Entity declaration
_ENTITY __entity_name IS PORT( __input_name, __input_name : IN STD_LOGIC; __input_vector_name : IN STD_LOGIC_VECTOR(__high downto _low); __bidir_name, __bidir_name : INOUT STD_LOGIC; __output_name, __output_name : OUT STD_LOGIC); END _entity_name;
----- For statement.
___loop_label: FOR __index_variable IN __range LOOP __statement; __statement; END LOOP _loop_label;
----- If statement.
_IF _expression THEN
___statement; __statement; ELSIF __expression THEN __statement; __statement; ELSE __statement; _statement; END IF;
----- Process with a sensitivity list.
___process_label: PROCESS (__signal_name, __signal_name, _signal_name) BEGIN
_END PROCESS _process_label;
----- Selected signal assignment. ( concurrent case statement )
___label: WITH __expression SELECT __signal <= __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN _constant_value;
------ Signal declaration.
_SIGNAL __signal_name : _type_name;
----- Signal assignment.
___signal_name <= _expression;
----- State machine with asynchronous reset.
_ENTITY __machine_name IS PORT( Clk : IN STD_LOGIC; Reset : IN STD_LOGIC; __input_name, __input_name : IN STD_LOGIC; __output_name, __output_name: OUT STD_LOGIC); END _machine_name;
_ARCHITECTURE a OF _machine_name IS
