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library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all; entity multiplexor is Port ( entrada1, entrada2, entrada3, entrada4,entrada5, entrada6, entrada7, entrada8 : in STD_LOGIC_VECTOR (6 downto 0); seleccion: in STD_LOGIC_VECTOR (2 downto 0); salida1: out STD_LOGIC_VECTOR (6 downto 0) ); end multiplexor; architecture Behavioral of multiplexor is begin with seleccion select salida1 <=entrada1 when "000", entrada2 when "001", entrada3 when "010", entrada4 when "011", entrada5 when "100", entrada6 when "101", entrada7 when "110", entrada8 when "111",
"0000000" when others; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Simulacion is -- end Simulacion; architecture Behavioral of Simulacion is component multiplexor Port ( entrada1, entrada2, entrada3, entrada4,entrada5, entrada6, entrada7, entrada8 : in STD_LOGIC_VECTOR (6 downto 0); seleccion: in STD_LOGIC_VECTOR (2 downto 0); salida1: out STD_LOGIC_VECTOR (6 downto 0) ); end component;
entrada2 <= "1111001"; entrada3 <= "1100110"; entrada4 <= "1110111"; entrada5 <= "1001010"; entrada6 <= "0110011"; entrada7 <= "1000011"; entrada8 <= "0110101"; seleccion <= "000"; wait for 100 ns; seleccion <= "001"; wait for 100 ns; seleccion <= "010"; wait for 100 ns; seleccion <= "011"; wait for 100 ns; seleccion <= "100"; wait for 100 ns; seleccion <= "101"; wait for 100 ns; seleccion <= "110"; wait for 100 ns; seleccion <= "111"; wait for 100 ns; wait; end process;
end Behavioral;
- /-/-/-///---/-/-//-/-/-/-/-/-/-/-/-/-/-/-/-/-/-/-/-/-/-/-/-/-/-/-/-/-* library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all; entity encoder is Port ( deco : in STD_LOGIC_VECTOR (3 downto 0); segmentos: out STD_LOGIC_VECTOR ( 6 downto 0) ); end decoder; architecture Behavioral of decoder is begin with deco select segmentos <= "0000 001 " when "000 0 ", " 1001111 " when "0 001 ", " 0010010 " when "0 01 0", " 0000110 " when "0 011 ",
-- Señales de salidas signal salida1 : STD_LOGIC_VECTOR (3 downto 0); begin UO: encoder Port map ( entrada => entrada, salida=> salida ); process begin --- Estímulos de la simulación wait for 100 ns; wait for 100 ns; entrada <= 0; wait for 100 ns; entrada <= 1; wait for 100 ns; entrada <= 2; wait for 100 ns; entrada <= 3; wait for 100 ns; entrada <= 4; seleccion <= "0100"; wait for 100 ns;
entrada <= 5; wait for 100 ns; entrada <= 6; wait for 100 ns; entrada <= 7; wait for 100 ns; entrada <= 8; wait for 100 ns; entrada <= 9; wait for 100 ns; wait; end process; end Behavioral; “#$%&$%&/()%(&/=)%/($%&/”%/”$%/$%&/#$%&/&$/()%&/()=&/() library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all;
"0010000" when "1110", "0111000" when "1111", "1111111" when others; end Behavioral; lklklklklklklklklklklklklklklklklkklklklklklkllkk library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Simulacion is -- end Simulacion; architecture Behavioral of Simulacion is component decoder Port ( deco : in STD_LOGIC_VECTOR (3 downto 0); segmentos: out STD_LOGIC_VECTOR (6 downto 0) ); end component; -- Señales de las entradas signal deco: STD_LOGIC_VECTOR (3 downto 0); -- Señales de salidas
signal salida1 : STD_LOGIC_VECTOR (6 downto 0); begin UO: encoder Port map ( deco => deco, segmentos=> segmentos ); process begin --- Estímulos de la simulación wait for 100 ns; wait for 100 ns; deco <= "0000"; wait for 100 ns; deco <= "0001"; wait for 100 ns; deco <= "0010"; wait for 100 ns; deco <= "0011"; wait for 100 ns; deco <= "0100"; wait for 100 ns; deco <= "0101";
deco <= "1111"; wait for 100 ns; wait; end process; end Behavioral; library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all; entity Alu5bits is Port ( A,B : in STD_LOGIC_VECTOR (4 downto 0); seleccion: in STD_LOGIC_VECTOR (1 downto 0); Result: out STD_LOGIC_VECTOR (4 downto 0) ); end Alu5bits; architecture Behavioral of Alu5bits is begin Result <= A + B when seleccion="00" else
A - B when seleccion="01" else A and B when seleccion="10" else A or B when seleccion="11"; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity Simulacion is -- end Simulacion; architecture Behavioral of Simulacion is component Alu5bits Port ( A,B : in STD_LOGIC_VECTOR (4 downto 0); seleccion: in STD_LOGIC_VECTOR (1 downto 0); Result: out STD_LOGIC_VECTOR (4 downto 0) ); end component; -- Señales de las entradas signal seleccion : STD_LOGIC_VECTOR (1 downto 0); signal A,B : STD_LOGIC_VECTOR (4 downto 0):= (others => '0'); -- Señales de salidas
B <= "00101";
wait for 100 ns; seleccion <= "11"; A <= "01000"; B <= "00101"; wait for 100 ns; wait; end process; end Behavioral; 435673456uyhedxrfcgty56djderu5 nuhje5r6 7e34d5rfgn ht6der4756bnrt ghfxcdre5r46 7 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all; entity sumas is Port ( A,B: in STD_LOGIC_VECTOR (4 downto 0); F: out STD_LOGIC_VECTOR (4 downto 0) ); end sumas; architecture Behavioral of sumas is
begin F <= A+B; end Behavioral; fr4 t5ft65 7de3c5brr6ftgy7uer4bv567n7cder4b56n7u8r45f6ty7u8jhn bmvfcrd456ty7u library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use IEEE.std_logic_unsigned.all; entity restas is Port ( A,B: in STD_LOGIC_VECTOR (4 downto 0); F: out STD_LOGIC_VECTOR (4 downto 0) ); end restas; architecture Behavioral of restas is begin F <= A-B; end Behavioral;
