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A A
B B
C C
D D
E E
1
1
2
2
3
3
4
4
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
1
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
1
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
1
Friday, January 06, 2012
Compal Electronics, Inc.
Intel Sandy/Ivy Bridge Processor with DDRIII + Panther Point PCH
Q5WV1 M/B Schematics Document
REV:0.
Compal Confidential
Nvidia N13P GS/GL
Compal ConfidentialModel Name :Q5WV1/Q5WS1Compal Project Name :File Name : LA-7912P
SCHEMATIC,MB A
4019ID
B
60
ZZZ2 X76344BOL
1G@ ZZZ2 X76344BOL
1G@
Part
Number
Description
DA60000SV
PCB
0N
LA-7912P
REV
M/B
MB PCB^ Part
Number
Description
DA60000SV
PCB
0N
LA-7912P
REV
M/B
MB PCB
ZZZ3 X76344BOL
2G@ ZZZ3 X76344BOL
2G@
A A
B B
C C
D D
E E
1
1
2
2
3
3
4
4
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
2
Friday, January 06,
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
2
Friday, January 06,
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
2
Friday, January 06, 2012
Compal Electronics, Inc.
USB port 10
USB port 13
USB port 11
100MHz
33MHz
100MHz
LS-7911P
DMI x4 100MHz1GB/s x
FDI x8 100MHz
page
41
port 3
port 1 Sub-board
page 39
page
13
SPI
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
RTC CKT.
page 13
3.3V 24MHz
LAN(GbE) &Card ReaderBCM
page 35,
MINI Card x
CMOS Camera
WLAN
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
Dual Channel
2.7GT/s
Power On/Off CKT.
Touch Pad
LPC BUS
page
41
Processor
Int.KBD
page
40
BANK 0, 1, 2, 3
USB 2.0 conn x
ALC271X/281X
DC/DC Interface CKT.
Sandy/Ivy Bridge
3.3V 48MHz
RJ
page
39
Fan Control
Power Circuit DC/DC
page 40
204pin DDRIII-SO-DIMM X
page 43,
Intel BIOS ROM
1.5V DDRIII 1066/
page
40
HDA Codec
Memory BUS(DDRIII)
PCH
HD Audio
page
42
page
4~
Panther Point-M
page
11,
page
ENE KB930/KB9012 40
page 36
page 37
page
38
page
38
page
31
rPGA
Intel
BluetoothConn
port 2
SATA CDROMConn.
page
34
SPI ROM x
page
41
page 46~
USBx
page
13~
port 0 page
34
SATA HDDConn.
USB 2.0/B 2PortUSB Port0,
Int. Speaker
Phone Jack x 2
USB port 0,1 onUSB/B
989pin BGA
PCI-E 2.0x
5GT/s PER LANE
100MHz
133MHz
LVDS Conn.
page 31
CRT Conn.
page 32
Nvidia N13P GS/GL
page22~
PEG(DIS)
page 33
HDMI Conn.
LVDS(UMA/OPTIMUS)CRT(UMA/OPTIMUS)TMDS(UMA/OPTIMUS)
USB 3.0 conn x1Fresco FL1009with USB3.0 Conn.
page 45
port 5
Card ReaderConn.
page 35,
LS-7912P
page 41
PWR/B
port 1
MSATA(WWAN)
page
34
USB port 8
port 2
eDP
page
SCHEMATIC,MB A
4019ID
60
B
5 5
4 4
3 3
2 2
1 1
EDP_COMP
PEG_COMP PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N
PEG_GTX_C_HRX_N
PEG_GTX_HRX_N15 PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P8PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P
PEG_GTX_C_HRX_P
PEG_GTX_HRX_P15PEG_GTX_HRX_P
PEG_GTX_C_HRX_P15 PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_N
PEG_HTX_C_GRX_N
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
PEG_HTX_GRX_P
PEG_HTX_C_GRX_P
EDP_HPD#
DMI_CTX_PRX_P <15>
DMI_CRX_PTX_P <15>
DMI_CTX_PRX_N <15>
DMI_CRX_PTX_N <15>
DMI_CTX_PRX_P <15>
DMI_CRX_PTX_P <15>
DMI_CTX_PRX_P <15>
DMI_CTX_PRX_N <15>
DMI_CRX_PTX_N <15>
DMI_CRX_PTX_P <15>
DMI_CTX_PRX_N <15>
DMI_CTX_PRX_P <15>
DMI_CRX_PTX_N <15>
DMI_CRX_PTX_N <15>
DMI_CRX_PTX_P <15>
DMI_CTX_PRX_N <15>
FDI_CTX_PRX_N <15>
FDI_CTX_PRX_N <15>
FDI_CTX_PRX_N <15>
FDI_CTX_PRX_N <15>
FDI_CTX_PRX_N <15>
FDI_CTX_PRX_N <15>
FDI_CTX_PRX_N <15>
FDI_CTX_PRX_N <15>
FDI_CTX_PRX_P <15>
FDI_CTX_PRX_P <15>
FDI_CTX_PRX_P <15>
FDI_CTX_PRX_P <15>
FDI_CTX_PRX_P <15>
FDI_CTX_PRX_P <15>
FDI_CTX_PRX_P <15>
FDI_CTX_PRX_P <15>
FDI_FSYNC <15>
FDI_FSYNC <15>
FDI_INT <15>
FDI_LSYNC <15>
FDI_LSYNC <15>
PEG_GTX_HRX_N[0..15]
<22>
PEG_HTX_C_GRX_P[0..15]
<22>
PEG_HTX_C_GRX_N[0..15]
<22>
PEG_GTX_HRX_P[0..15]
<22>
EDP_HPD# <31>
EDP_AUXP <31>
EDP_AUXN <31>
EDP_TXP <31>
EDP_TXP <31>
EDP_TXN <31>
EDP_TXN <31>
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
4
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
4
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
4
Friday, January 06, 2012
Compal Electronics, Inc.
Typ- suggest 220nF. The change in AC capacitorvalue from 100nF to 220nF is to enablecompatibility with future platforms having PCIEGen3 (8GT/s)
eDP_COMPIO
and
ICOMPO
signals should
be shorted
near
balls,
Trace Width
for
EDP_COMPIO=4mils,
EDP_ICOMPO=12mils,and both
length
less
than 500 mils...
should not
be
left
floating
,even if
disable
eDP
function...
PEG_ICOMPI and PEG_RCOMPO signals should beshorted and routed,max length = 500 mils,trace width=4milsPEG_ICOMPO signals should be routed with - maxlength = 500 mils,trace width=12milsspacing =15mils
Add eDP circuit
SCHEMATIC,MB A
4019ID
60
B
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
R8091K_0402_5% EDP@
R8091K_0402_5% EDP@
1 2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
GRAPHICS - EXPRESS* PCI
DMI Intel(R) FDI eDP
JCPU1A TYCO_2013620-2_IVY BRIDGECONN@
GRAPHICS - EXPRESS* PCI
DMI Intel(R) FDI eDP
JCPU1ADMI_RX#[0] TYCO_2013620-2_IVY BRIDGECONN@ B
DMI_RX#[1] B
DMI_RX#[2] A
DMI_RX#[3] B
DMI_RX[0] B
DMI_RX[1] B
DMI_RX[2] A
DMI_RX[3] B
DMI_TX#[0]
G
DMI_TX#[1]
E
DMI_TX#[2]
F
DMI_TX#[3]
D
DMI_TX[0]
G
DMI_TX[1]
D
DMI_TX[3] C
DMI_TX[2]
F
FDI0_TX#[0] A
FDI0_TX#[1]
H
FDI0_TX#[2]
E
FDI0_TX#[3]
F
FDI1_TX#[0] B
FDI1_TX#[1] C
FDI1_TX#[2]
D
FDI1_TX#[3]
E
FDI0_TX[0] A
FDI0_TX[1]
G
FDI0_TX[2]
E
FDI0_TX[3]
G
FDI1_TX[0] B
FDI1_TX[1] C
FDI1_TX[2]
D
FDI1_TX[3]
F
FDI0_FSYNC
J
FDI1_FSYNC
J
FDI_INT
H
FDI0_LSYNC J
FDI1_LSYNC
H
PEG_ICOMPI
J
PEG_ICOMPO
J
PEG_RCOMPO
H
PEG_RX#[0]
K
PEG_RX#[1]
M
PEG_RX#[2]
L
PEG_RX#[3]
J
PEG_RX#[4]
J
PEG_RX#[5]
H
PEG_RX#[6]
H
PEG_RX#[7]
G
PEG_RX#[8]
G
PEG_RX#[9]
F
PEG_RX#[10]
E
PEG_RX#[11]
E
PEG_RX#[12]
D
PEG_RX#[13]
D
PEG_RX#[14]
B
PEG_RX#[15]
C
PEG_RX[0]
J
PEG_RX[1]
L
PEG_RX[2]
K
PEG_RX[3]
H
PEG_RX[4]
H
PEG_RX[5]
G
PEG_RX[6]
G
PEG_RX[7]
F
PEG_RX[8]
F
PEG_RX[9]
E
PEG_RX[10]
E
PEG_RX[11]
F
PEG_RX[12]
D
PEG_RX[13]
E
PEG_RX[14]
C
PEG_RX[15]
B
PEG_TX#[0]
M
PEG_TX#[1]
M
PEG_TX#[2]
M
PEG_TX#[3]
L
PEG_TX#[4]
L
PEG_TX#[5]
K
PEG_TX#[6]
K
PEG_TX#[7]
J
PEG_TX#[8]
J
PEG_TX#[9]
H
PEG_TX#[10]
G
PEG_TX#[11]
E
PEG_TX#[12]
F
PEG_TX#[13]
D
PEG_TX#[14]
F
PEG_TX#[15]
E
PEG_TX[0]
M
PEG_TX[1]
M
PEG_TX[2]
M
PEG_TX[3]
L
PEG_TX[4]
L
PEG_TX[5]
K
PEG_TX[6]
K
PEG_TX[7]
J
PEG_TX[8]
J
PEG_TX[9]
H
PEG_TX[10]
G
PEG_TX[11]
E
PEG_TX[12]
F
PEG_TX[13]
D
PEG_TX[14]
E
PEG_TX[15]
D
eDP_AUX C
eDP_AUX# D
eDP_TX[0] C
eDP_TX[1] F
eDP_TX[2] C
eDP_TX[3] G
eDP_TX#[0] C
eDP_TX#[1] E
eDP_TX#[2] D
eDP_TX#[3] F
eDP_COMPIO A
eDP_HPD# B
eDP_ICOMPO A
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
R145R14524.9_0402_1%24.9_0402_1% 1 2
R 24.9_0402_1%
R 24.9_0402_1%
1 2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K DIS@
C
0.22U_0402_10V6K DIS@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
C
0.22U_0402_10V6K GSGL@
C
0.22U_0402_10V6K GSGL@ 1
2
5 5
4 4
3 3
2 2
1 1
H_CATERR#
CLK_CPU_DMICLK_CPU_DMI#
H_PROCHOT#_RH_THRMTRIP# H_PM_SYNC PM_DRAM_PWRGD_R
BUF_CPU_RST#
SM_DRAMRST#SM_RCOMP0SM_RCOMP1SM_RCOMP
H_PECI
H_PROCHOT#
BUFO_CPU_RST#
PLT_RST#
H_CPUPWRGD
XDP_DBRESET#
TCKTMSTRST#TDITDO
CLK_CPU_DPLLCLK_CPU_DPLL#
CLK_CPU_DPLLCLK_CPU_DPLL#
PM_DRAM_PWRGD_R
PM_SYS_PWRGD_BUF
BUF_CPU_RST#BUF_CPU_RST#
H_PECI <18,40>
H_SNB_IVB# <17> H_PM_SYNC H_THRMTRIP# <15> <18> H_CPUPWRGD <18>
H_PROCHOT# <40,46>
SM_DRAMRST#
<6> CLK_CPU_DMI#
<14>
CLK_CPU_DMI
<14>
PLT_RST# <17>
XDP_DBRESET#
<15>
CLK_CPU_DPLL
<14>
CLK_CPU_DPLL#
<14>
PM_DRAM_PWRGD <15>
SYS_PWROK <15>
+1.05VS_VTT
+3VS
+1.05VS_VTT
+3VS
+1.05VS_VTT
+3VALW
+1.5VS
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
5
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
5
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
5
Friday, January 06, 2012
Compal Electronics, Inc.
DDR
Compensation
Signals
Processor Pullups
SNB_IVB#
had
changed
the
name
to
PROC_SELCT#,function
for
future
platform,
connect
to
the
DF_TVS
strap
on
the
PCH
UNCOREPWRGOOD: SM_DRAMPWROK:DRAM power ok
CORE
OK
Buffered reset to CPU
RESET#:
ok
CPU
reset
For
LVDS
If
use
External
Graphic
or
use
integrated
without
eDP
DPLL_REF_SSCLK
PD
1K_5%
to
GND
DPLL_REF_SSCLK#
PH
1K_5%
to
+1.05VS_VTT
For
eDP
R
modify
SCHEMATIC,MB A
4019ID
60
B
R40R401K_0402_5%1K_0402_5% 1 2
T
PAD
@
T
PAD
@
R
62_0402_5%
R
62_0402_5% 1
2
T
PAD
@
T
PAD
@
R
10K_0402_5%
R
10K_0402_5% 1
2
T
PAD
@
T
PAD
@
T
PAD
@
T
PAD
@ U11U1174AHC1G09GW_TSSOP574AHC1G09GW_TSSOP B 1
A 2
OG 3
(^4) 5 P
R
130_0402_5%
R
130_0402_5% 1
2
R
140_0402_1%
R
140_0402_1% 1
2
R87R8743_0402_1%43_0402_1% 1
2
R
1K_0402_5%
LVDS@
R
1K_0402_5%
LVDS@ 1 2
R 56_0402_5%
R 56_0402_5%^1
2
1 C162C1620.1U_0402_16V4Z0.1U_0402_16V4Z 2 U7U7 SN74LVC1G07DCKR_SC70-5SN74LVC1G07DCKR_SC70-
NC 1
A 2
G 3
Y^
4 5 P
R
200_0402_1%
R
200_0402_1% 1
2
C
0.1U_0402_16V4Z
C
0.1U_0402_16V4Z
1 2
CLOCKS
MISC THERMAL PWR MANAGEMENT
DDR
MISC JTAG & BPM
JCPU1B TYCO_2013620-2_IVY BRIDGECONN@
CLOCKS
MISC THERMAL PWR MANAGEMENT
DDR
MISC JTAG & BPM
JCPU1B TYCO_2013620-2_IVY BRIDGECONN@
SM_RCOMP[1]
A
SM_RCOMP[2]
A
SM_DRAMRST#
R
SM_RCOMP[0]
AK BCLK#
A BCLK
A
DPLL_REF_CLK#
A
DPLL_REF_CLK
A
CATERR#
AL
PECI
AN
PROCHOT#
AL
THERMTRIP#
AN
SM_DRAMPWROK V
RESET# AR
PRDY#
AP
PREQ#
AP TCK
AR TMS
AR TRST#
AP TDI
AR TDO
AP DBR#
AL
BPM#[0]
AT
BPM#[1]
AR
BPM#[2]
AR
BPM#[3]
AT
BPM#[4]
AP
BPM#[5]
AR
BPM#[6]
AT
BPM#[7]
AR
PM_SYNC
AM
SKTOCC#
AN
PROC_SELECT# C
UNCOREPWRGOOD AP
R
1K_0402_5%
LVDS@
R
1K_0402_5%
LVDS@ 1 2
R
25.5_0402_1%
R
25.5_0402_1% 1
T
PAD
@ T PAD
@ T PAD
@ T PAD
@
R205R205200_0402_1%200_0402_1% 1 2
R203R20339_0402_1%39_0402_1%@@ 1 2
1 R90R9075_0402_1%75_0402_1% 2
C?C?0.1U_0402_16V4Z0.1U_0402_16V4Z 2 1
1 @@R88R880_0402_5%0_0402_5% 2
5 5
4 4
3 3
2 2
1 1
VSSAXG_VAL_SENSE
CFG2 CFG4 CFG6CFG5 CFG
VCC_VAL_SENSE
CFG0CFG2CFG4CFG5CFG6CFG VAXG_VAL_SENSEVSS_VAL_SENSE
+CPU_CORE +VGFX_CORE
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
7
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
7
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
7
Friday, January 06, 2012
Compal Electronics, Inc.
AH
change
to
VCC_DIE_SENSE
10:
x8,
x
Device
1
function
1
enabled
;
function
2
disabled
PCIE
Port
Bifurcation
Straps
CFG[6:5]
11:
(Default)
x
Device
1
functions
1
and
2
disabled
PEG^ CFG
DEFER
TRAINING^ 0:
PEG
Wait
for
BIOS
for
training
1:
(Default)
PEG
Train
immediately
following
xxRESETB
de
assertion
Display CFG
Port
Presence
Strap
0
:^
Enabled;
An
external
Display
Port
device
is
connected
to
the
Embedded
Display
Port
1
:^
Disabled;
No
Physical
Display
Port
attached
to
Embedded
Display
Port
CFG Straps for Processor
01:
Reserved
(Device
1
function
1
disabled
;
function
2
enabled)
00:
x8,x4,x
Device
1
functions
1
and
2
enabled
PEG
Static
Lane
Reversal
-^
CFG
is
for
the
16x
CFG
0:Lane
Reversed
1:
Normal
Operation;
Lane
definition
matches
socket
pin
map
definition
AH
Sandy
Ivy VSS_DIE_SENSE
GND
RSVD
and
RSVD
had
changed
to
BCLK_ITP
and
BCLK_ITP#
SCHEMATIC,MB A
4019ID
60
B
T PAD @^
T PAD @
R 49.9_0402_1%
R810@ 49.9_0402_1%
@
2 1
2 R813R813@@49.9_0402_1%49.9_0402_1% 1
R1081K_0402_5% @
R1081K_0402_5% (^1) @ 2
R 1K_0402_5%
GM@R 1K_0402_5%
GM@
1 2
R 49.9_0402_1%
R812@ 49.9_0402_1%
@
2 1
2 R811R811@@49.9_0402_1%49.9_0402_1% 1
RESERVED CFG
JCPU1E TYCO_2013620-2_IVY BRIDGECONN@
RESERVED CFG
JCPU1E CFG[0] TYCO_2013620-2_IVY BRIDGECONN@ AK
CFG[1] AK
CFG[2] AL
CFG[3] AL
CFG[4] AK
CFG[5] AL
CFG[6] AL
CFG[7] AM
CFG[8] AM
CFG[9] AM
CFG[10] AM
CFG[11] AM
CFG[12] AN
CFG[13] AN
CFG[14] AN
CFG[15] AM
CFG[16] AK
CFG[17] AN
RSVD
AM
RSVD
AJ
RSVD
J
RSVD_NCTF
AT
RSVD
H
RSVD
G
RSVD_NCTF
AR
RSVD_NCTF
AT
RSVD_NCTF
AR
RSVD_NCTF
AT
RSVD_NCTF
AT
RSVD_NCTF
AR
RSVD_NCTF
B
RSVD_NCTF
A
RSVD_NCTF
A
RSVD_NCTF
B
RSVD_NCTF
C
RSVD
AJ
RSVD
AK
RSVD J
RSVD C
RSVD D
RSVD A
RSVD B
RSVD D
RSVD B
RSVD A
RSVD B
RSVD C
RSVD
T
RSVD F
RSVD F
RSVD D
RSVD G
RSVD G
RSVD E
RSVD
W
RSVD
AT
RSVD_NCTF
AP
RSVD F
RSVD AJ
VAXG_VAL_SENSE AJ
VSSAXG_VAL_SENSE AH
VCC_VAL_SENSE AJ
VSS_VAL_SENSE AH
KEY
B
VCC_DIE_SENSE
AH
BCLK_ITP
AN
BCLK_ITP#
AM
VSS_DIE_SENSE
AH
RSVD
AK
RSVD
AE
RSVD
AG
RSVD
L
RSVD J
RSVD B
R1021K_0402_5% @
R1021K_0402_5% @ 1 EDP@EDP@R109R1091K_0402_5%1K_0402_5% 2 1 2
T^
PAD@ T^
PAD@
1 R112R1121K_0402_5%1K_0402_5% 2
T PAD @^
T PAD @
5 5
4 4
3 3
2 2
1 1
H_CPU_SVIDALRT#H_CPU_SVIDCLKH_CPU_SVIDDAT VCCSENSE_RVSSSENSE_RVSSIO_SENSE
VCCIO_SENSE
<50>
VCCSENSE
<52>
VSSSENSE
<52>
VR_SVID_ALRT#
<52>
VR_SVID_CLK
<52>
VR_SVID_DAT
<52>
VSSIO_SENSE
<50>
+1.05VS_VTT
+1.05VS_VTT
+CPU_CORE
+1.05VS_VTT
+CPU_CORE
+1.05VS_VTT
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
8
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
8
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
8
Friday, January 06, 2012
Compal Electronics, Inc.
8.5A
QC
53A DC
53A
SV
type
CPU
Should change to connect formpower cirucit & layout differentialwith VCCIO_SENSE.
Place
the
PU
resistors
close
to
CPU
VSSIO_SENSEchange
to
VSS_SENSE_VCCIO
SCHEMATIC,MB A
4019ID
60
B
1 R163R16310_0402_5%10_0402_5% 2
R445R445100_0402_1%100_0402_1% 1 2
R448R44843_0402_1%43_0402_1% 1
2
R447R44775_0402_5%75_0402_5% 1 2
R
10_0402_5%
R
10_0402_5% 1
2
R
0_0402_5%
R
0_0402_5%
1
2
R
0_0402_5%
R
0_0402_5%
1
2
POWER
CORE SUPPLY
PEG AND DDR SVID SENSE LINES
JCPU1F TYCO_2013620-2_IVY BRIDGE
CONN@
POWER
CORE SUPPLY
PEG AND DDR SVID SENSE LINES
JCPU1F TYCO_2013620-2_IVY BRIDGE
CONN@
VCC_SENSE
AJ
VSS_SENSE
AJ
VIDALERT#
AJ
VIDSCLK
AJ
VIDSOUT
AJ
VSS_SENSE_VCCIO
A
VCC AG
VCC AG
VCC AG
VCC AG
VCC AG
VCC AG
VCC AG
VCC AG
VCC AG
VCC AG
VCC AF
VCC AF
VCC AF
VCC AF
VCC AF
VCC AF
VCC AF
VCC AF
VCC AF
VCC AF
VCC AD
VCC AD
VCC AD
VCC AD
VCC AD
VCC AD
VCC AD
VCC AD
VCC AD
VCC AD
VCC
AC
VCC
AC
VCC
AC
VCC
AC
VCC AC
VCC AC
VCC AC
VCC AC
VCC AC
VCC AC
VCC AA
VCC AA
VCC AA
VCC AA
VCC AA
VCC AA
VCC AA
VCC AA
VCC AA
VCC AA
VCC Y
VCC Y
VCC Y
VCC Y
VCC Y
VCC Y
VCC Y
VCC Y
VCC Y
VCC Y
VCC V
VCC V
VCC V
VCC V
VCC V
VCC V
VCC V
VCC V
VCC V
VCC V
VCC U
VCC U
VCC U
VCC U
VCC U
VCC U
VCC U
VCC U
VCC U
VCC U
VCC R
VCC R
VCC R
VCC R
VCC R
VCC R
VCC R
VCC R
VCC R
VCC R
VCC P
VCC P
VCC P
VCC P
VCC P
VCC P
VCC P
VCC P
VCC P
VCC P
VCCIO
AH
VCCIO
J
VCCIO
G
VCCIO
F
VCCIO
F
VCCIO
F
VCCIO
F
VCCIO
E
VCCIO
E
VCCIO
AH
VCCIO
AG
VCCIO
AC
VCCIO
Y
VCCIO
U
VCCIO
P
VCCIO
L
VCCIO
J
VCCIO
J
VCCIO
J
VCCIO
H
VCCIO
H
VCCIO
H
VCCIO
G
VCCIO
G
VCCIO
E
VCCIO
C
VCCIO
C
VCCIO
B
VCCIO
B
VCCIO
A
VCCIO
A
VCCIO
A
VCCIO
A
VCCIO
D
VCCIO
D
VCCIO
D
VCCIO
D
VCCIO
C
VCCIO
C
VCCIO_SENSE
B
VCCIO
J
R
0_0402_5%
R
0_0402_5%
1
2
R
0_0402_5%
R
0_0402_5%
1
2
R 130_0402_1%
R 130_0402_1%
1 2
R442R442100_0402_1%100_0402_1% 1 2
4 4 3 3 2 2 1 1 TitleSize Document Number Rev Date: Sheet of
Security Classification
Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom Compal Electronics, Inc. TitleSize Document Number Rev Date: Sheet of
Security Classification
Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom Compal Electronics, Inc. TitleSize Document Number Rev Date: Sheet of
Security Classification
Compal Secret Data THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom 4019ID 60
B
VSS JCPU1I TYCO_2013620-2_IVY BRIDGECONN@ VSS VSS JCPU1H TYCO_2013620-2_IVY BRIDGECONN@ VSS
- Friday, January 06, - 2011/06/ - 2012/06/ - Friday, January 06, - 2011/06/ - 2012/06/ - Friday, January 06, - 2011/06/ - 2012/06/ - Compal Electronics, Inc. SCHEMATIC,MB A - T JCPU1I VSS161 TYCO_2013620-2_IVY BRIDGECONN@ - VSS - T - VSS - T - VSS - T - VSS - T - VSS - T - VSS - T - VSS - T - VSS - T - VSS - T - VSS - P - VSS - P - VSS - P - VSS - P - VSS - P - VSS - P - VSS - N - VSS - N - VSS - N - VSS - N - VSS - N - VSS - N - VSS - N - VSS - N - VSS - N - VSS - N - VSS - M - VSS - L - VSS - L - VSS - L - VSS - L - VSS - L - VSS - L - VSS - L - VSS - L - VSS - L - VSS - L - VSS - L - VSS - K - VSS - K - VSS - K - VSS - K - VSS - J - VSS - J - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - H - VSS - G - VSS - G - VSS - G - VSS - G - VSS - G - VSS - G - VSS - G - VSS - G - VSS - F - VSS - F - VSS - F - VSS - F - VSS - F - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - E - VSS - D - VSS - D - VSS - D - VSS - D - VSS - D - VSS - D - VSS - C - VSS - C - VSS - C - VSS - C - VSS - C - VSS - C - VSS - C - VSS - C - VSS - B - VSS - B - VSS - B - VSS - B - VSS - B - VSS - B - VSS - B - VSS - B - VSS - B - VSS - B - VSS - B - VSS - B - VSS - A - VSS - A - VSS - A - VSS - A - VSS - A - VSS - A - VSS - A
- AT JCPU1HVSS1 TYCO_2013620-2_IVY BRIDGECONN@ - VSS - AT - VSS - AT - VSS - AT - VSS - AT - VSS - AT - VSS - AT - VSS - AT - VSS - AT - VSS - AT - VSS - AT - VSS - AT - VSS - AT - VSS - AR - VSS - AR - VSS - AR - VSS - AR - VSS - AR - VSS - AR - VSS - AR - VSS - AR - VSS - AR - VSS - AP - VSS - AP - VSS - AP - VSS - AP - VSS - AP - VSS - AP - VSS - AP - VSS - AP - VSS - AP - VSS - AP - VSS - AP - VSS - AP - VSS - AN - VSS - AN - VSS - AN - VSS - AN - VSS - AN - VSS - AN - VSS - AN - VSS - AN - VSS - AN - VSS - AN - VSS - AM - VSS - AM - VSS - AM - VSS - AM - VSS - AM - VSS - AM - VSS - AM - VSS - AM - VSS - AM - VSS - AM - VSS - AM - VSS - AM - VSS - AL - VSS - AL - VSS - AL - VSS - AL - VSS - AL - VSS - AL - VSS - AL - VSS - AL - VSS - AL - VSS - AL - VSS - AL - VSS - AL - VSS - AK - VSS - AK - VSS - AK - VSS - AK - VSS - AK - VSS - AK - VSS - AK - VSS - AK - VSS - AK - VSS - AK - VSS - AK - VSS - AJ
- AJ - VSS - AJ - VSS - AJ - VSS - AJ - VSS - AJ - VSS - AJ - VSS - AJ - VSS - AJ - VSS - AJ - VSS - AJ - VSS - AH - VSS - AH - VSS - AH - VSS - AH - VSS - AH - VSS - AH - VSS - AH - VSS - AH - VSS - AH - VSS - AH - VSS - AH - VSS - AH - VSS - AG - VSS - AG - VSS - AG - VSS - AF - VSS - AF - VSS - AF - VSS - AF - VSS - AE - VSS - AE - VSS - AE - VSS - AE - VSS - AE - VSS - AE - VSS - AE - VSS - AE - VSS - AE - VSS - AE - VSS - AE - VSS - AD - VSS - AC - VSS - AC - VSS - AC - VSS - AC - VSS - AC - VSS - AC - VSS - AB - VSS - AB - VSS - AB - VSS - AB - VSS - AB - VSS - AB - VSS - AB - VSS - AB - VSS - AB - VSS - AB - VSS - Y - VSS - Y - VSS - Y - VSS - Y - VSS - Y - VSS - Y - VSS - W - VSS - W - VSS - W - VSS - W - VSS - W - VSS - W - VSS - W - VSS - W - VSS - W - VSS - W - VSS - U - VSS - U - VSS - U - VSS - U - VSS - U - VSS - U
5 5
4 4
3 3
2 2
1 1
+V_DDR_REFADDR_A_D0DDR_A_D1DDR_A0_DM0DDR_A_D2DDR_A_D3DDR_A_D8DDR_A_D9DDR_A_DQS#1DDR_A_DQS1DDR_A_D10DDR_A_D11DDR_A_D16DDR_A_D17DDR_A_DQS#2DDR_A_DQS2DDR_A_D18DDR_A_D19DDR_A_D24DDR_A_D25DDR_A0_DM3DDR_A_D26DDR_A_D27 DDR_A_MA12DDR_A_MA9DDR_A_MA8DDR_A_MA5DDR_A_MA3DDR_A_MA1DDR_A_MA10DDR_A_BS0DDR_A_MA13DDR_A_D32DDR_A_DQS#4DDR_A_DQS4DDR_A_D34DDR_A_D35DDR_A_D40DDR_A_D41DDR_A0_DM5DDR_A_D42DDR_A_D43DDR_A_D49DDR_A_DQS#6DDR_A_DQS6DDR_A_D50DDR_A_D51DDR_A_D56DDR_A_D57DDR_A0_DM7DDR_A_D58DDR_A_D DDR_A_BS2 DDRA_CS1_DIMMA#
SA_CLK_DDR0SA_CLK_DDR# DDRA_CKE0_DIMMA
DDR_A_WE#DDR_A_CAS# DDR_A_D33 DDR_A_D
DDRA_CKE1_DIMMADDR_A_MA15DDR_A_MA14DDR_A_MA11DDR_A_MA7DDR_A_MA6DDR_A_MA4DDR_A_MA2DDR_A_MA0SA_CLK_DDR1SA_CLK_DDR#1DDR_A_BS1DDR_A_RAS#DDRA_CS0_DIMMA#SA_ODT0SA_ODT1DDR_A_D36DDR_A_D37DDR_A0_DM4DDR_A_D45DDR_A_DQS#5DDR_A_DQS5DDR_A_D46DDR_A_D52DDR_A_D53DDR_A0_DM6DDR_A_D55DDR_A_D60DDR_A_D61DDR_A_DQS#7DDR_A_DQS7DDR_A_D62DDR_A_D63D_CK_SDATAD_CK_SCLK
+VREF_CA
DDR_A_D4DDR_A_D5DDR_A_DQS#0DDR_A_DQS0DDR_A_D6DDR_A_D7DDR_A_D12DDR_A_D13DDR_A0_DM1DDR_A_D14DDR_A_D15DDR_A_D20DDR_A_D21DDR_A0_DM2DDR_A_D22DDR_A_D23DDR_A_D28DDR_A_D29DDR_A_DQS#3DDR_A_DQS3DDR_A_D30DDR_A_D31 DDR_A_D38DDR_A_D39DDR_A_D44 DDR_A_D47 DDR_A_D
DDR_A0_DM0DDR_A0_DM1DDR_A0_DM2DDR_A0_DM3DDR_A0_DM4DDR_A0_DM5DDR_A0_DM6DDR_A0_DM
DDR3_DRAMRST#
DDRA_CS1_DIMMA# <6>
DDR_A_CAS# <6>
DDR_A_WE# <6>
DDR_A_BS SA_CLK_DDR0<6>SA_CLK_DDR#0<6> <6> DDR_A_BS DDRA_CKE0_DIMMA<6> <6>
DDRA_CKE1_DIMMA
<6>
SA_CLK_DDR
<6>
SA_CLK_DDR#
<6>
DDR_A_BS
<6>
DDR_A_RAS#
<6>
DDRA_CS0_DIMMA#
<6>
SA_ODT
<6> SA_ODT
<6>
D_CK_SDATA
<12,14,41>
D_CK_SCLK
<12,14,41>
DIMM_DRAMRST#
<6,12>
RST_GATE
<6,12,14>
SA_DIMM_VREFDQ <9>
DDR_A_D[0..63]
<6>
DDR_A_DQS[0..7]
<6>
DDR_A_DQS#[0..7]
<6>
DDR_A_MA[0..15]
<6>
+1.5V
+3VS+0.75VS
+0.75VS
+1.5V
+1.5V
+1.5V
+1.5V +1.5V +1.5V +0.75VS TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
11
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
11
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
11
Friday, January 06, 2012
Compal Electronics, Inc.
All VREF traces shouldhave 10 mil trace width
DIMM_1 Reserve H:8mm
M3 support
Layout
Note:
Place
near
JDIMM1.203,
CHG C407 to oscon
Layout
Note:
Place
near
JDIMM
R^
modify
for
ESD
SCHEMATIC,MB A
4019ID
60
B
1 R267R2671K_0402_5%1K_0402_5% 2
C3851U_0402_6.3V6KC3851U_0402_6.3V6K 1 2
2.2U_0603_6.3V6K2.2U_0603_6.3V6KC408C 1 2
C20660.1U_0402_16V4ZC20660.1U_0402_16V4Z 1 2
10U_0603_6.3V6M10U_0603_6.3V6MC383C383@@ 1 2
C41410U_0603_6.3V6MC41410U_0603_6.3V6M 1 2
C41310U_0603_6.3V6MC41310U_0603_6.3V6M 1 2
2.2U_0603_6.3V6K2.2U_0603_6.3V6KC372C 1 2
R30210K_0402_5%R30210K_0402_5% 1 2
330U_D2_2V_Y@^ C
330U_D2_2V_Y@^ C 1 2
C3730.1U_0402_16V4ZC3730.1U_0402_16V4Z 1 2
C3951U_0402_6.3V6KC3951U_0402_6.3V6K 1 2
R133@ R133@0_0402_5%0_0402_5% 1
2
C3941U_0402_6.3V6KC3941U_0402_6.3V6K 1 2
C4040.1U_0402_16V4ZC4040.1U_0402_16V4Z 1 2
1 R266R2661K_0402_5%1K_0402_5% 2
1 R320R3201K_0402_5%1K_0402_5% 2
C4091U_0402_6.3V6KC4091U_0402_6.3V6K 1 2
R30110K_0402_5%R30110K_0402_5% 2 1
C41210U_0603_6.3V6MC41210U_0603_6.3V6M 1 2
G
D S
Q
S TR SSM3K7002F 1N SC59-
@ G
D S
Q
S TR SSM3K7002F 1N SC59-
(^1) @ 2 3
C41510U_0603_6.3V6MC41510U_0603_6.3V6M 1 2
C3711U_0402_6.3V6KC3711U_0402_6.3V6K 1 2
C3881U_0402_6.3V6KC3881U_0402_6.3V6K 1 2 C4101U_0402_6.3V6KC4101U_0402_6.3V6K 1 2
C4162.2U_0603_6.3V6KC4162.2U_0603_6.3V6K 1 2
C38410U_0603_6.3V6MC38410U_0603_6.3V6M 1 2
1 R319R3191K_0402_5%1K_0402_5% 2
C3931U_0402_6.3V6KC3931U_0402_6.3V6K 1 2
0.1U_0402_16V4Z0.1U_0402_16V4ZC411C 1 2
JDIMM1JDIMM1 1 VREF_DQ FOX_AS0A626-U8SN-7FFOX_AS0A626-U8SN-7FCONN@CONN@
VSS
(^2)
VSS 3
DQ
(^4)
DQ 5
DQ
(^6)
DQ 7
VSS
(^8)
VSS 9
DQS#
(^10)
DM 11
DQS
(^12)
VSS 13
VSS
(^14)
DQ 15
DQ
(^16)
DQ 17
DQ
(^18)
VSS 19
VSS
(^20)
DQ 21
DQ
(^22)
DQ 23
DQ
(^24)
VSS 25
VSS
(^26)
DQS# 27
DM
(^28)
DQS 29
RESET#
(^30)
VSS 31
VSS
(^32)
DQ 33
DQ
(^34)
DQ 35
DQ
(^36)
VSS 37
VSS
(^38)
DQ 39
DQ
(^40)
DQ 41
DQ
(^42)
VSS 43
VSS
(^44)
DQS# 45
DM
(^46)
DQS 47
VSS
(^48)
VSS 49
DQ
(^50)
DQ 51
DQ
(^52)
DQ 53
VSS
(^54)
VSS 55
DQ
(^56)
DQ 57
DQ
(^58)
DQ 59
VSS
(^60)
VSS 61
DQS#
(^62)
DM 63
DQS
(^64)
VSS 65
VSS
(^66)
DQ 67
DQ
(^68)
DQ 69
DQ
(^70)
VSS 71
VSS
(^72)
A12/BC# 83
A
(^84)
A 85
A^
86
VDD 87
VDD
(^88)
A 89
A^
90
CKE 73
CKE
(^74)
VDD 75
VDD
(^76)
NC 77
A
(^78)
BA 79
A
(^80)
VDD 81
VDD
(^82)
A 91
A^
92
VDD 93
VDD
(^94)
A 95
A^
96
A 97
A^
98
VDD 99
VDD
(^100)
CK 101
CK
(^102)
CK0# 103
CK1#
(^104)
VDD 105
VDD
(^106)
A10/AP 107
BA
(^108)
BA 109
RAS#
(^110)
VDD 111
VDD
(^112)
WE# 113
S0#
(^114)
CAS# 115
ODT
(^116)
VDD 117
VDD
(^118)
A 119
ODT
(^120)
S1# 121
NC
(^122)
VDD 123
VDD
(^124)
NCTEST 125
VREF_CA
(^126)
VSS 127
VSS
(^128)
DQ 129
DQ
(^130)
DQ 131
DQ
(^132)
VSS 133
VSS
(^134)
DQS# 135
DM
(^136)
DQS 137
VSS
(^138)
VSS 139
DQ
(^140)
DQ 141
DQ
(^142)
DQ 143
VSS
(^144)
VSS 145
DQ
(^146)
DQ 147
DQ
(^148)
DQ 149
VSS
(^150)
VSS 151
DQS#
(^152)
DM 153
DQS
(^154)
VSS 155
VSS
(^156)
DQ 157
DQ
(^158)
DQ 159
DQ
(^160)
VSS 161
VSS
(^162)
DQ 163
DQ
(^164)
DQ 165
DQ
(^166)
VSS 167
VSS
(^168)
DQS# 169
DM
(^170)
DQS 171
VSS
(^172)
VSS 173
DQ
(^174)
DQ 175
DQ
(^176)
DQ 177
VSS
(^178)
VSS 179
DQ
(^180)
DQ 181
DQ
(^182)
DQ 183
VSS
(^184)
VSS 185
DQS#
(^186)
DM 187
DQS
(^188)
VSS 189
VSS
(^190)
DQ 191
DQ
(^192)
DQ 193
DQ
(^194)
VSS 195
VSS
(^196)
SA 197
EVENT#
(^198)
VDDSPD 199
SDA
(^200)
SA 201
SCL
(^202)
VTT 203
VTT
(^204)
G 205
G^
206
C37810U_0603_6.3V6MC37810U_0603_6.3V6M 1 2
5 5
4 4
3 3
2 2
1 1
PCH_RTCX1PCH_RTCX
PCH_RTCX1PCH_RTCRST#SM_INTRUDER#PCH_INTVRMEN
SM_INTRUDER#
PCH_SPKR PCH_SPI_MOSIPCH_SPI_MISO
PCH_SPI_CS0#_
PCH_JTAG_TCK
PCH_SATALED#
PCH_RTCX2PCH_SRTCRST#HDA_BITCLK_PCHHDA_SYNC_PCHHDA_RST_PCH#HDA_SDIN0 HDA_SDOUT_PCH PCH_JTAG_TMSPCH_JTAG_TDIPCH_JTAG_TDO
LPC_AD0LPC_AD1LPC_AD2LPC_AD3LPC_FRAME#SERIRQ SATA_COMPSATA3_COMPRBIAS_SATA3 PCH_GPIO
PCH_INTVRMEN HDA_BITCLK_PCHHDA_RST_PCH#HDA_SDOUT_PCH
PCH_SPKR HDA_SDOUT_PCH HDA_SYNC_PCH HDA_SYNC_PCH_R
PCH_SPI_CLK_1PCH_SPI_MOSI_1PCH_SPI_MISO_
SGEN#
SERIRQPCH_SATALED#PCH_GPIO
+RTCBATT_R
PCH_SPI_MISO_
PCH_SPI_CS0#_
PCH_SPI_CLK_1PCH_SPI_MOSI_1SPI_WP1#SPI_HOLD1#
SPI_WP1#SPI_HOLD1#
PCH_SPI_CLK_
SGEN#
HDA_SYNC_PCH
HDA_SYNC_PCH_R
PCH_SPI_CLK_
PCH_SPI_CLK
PCH_SPI_CS0#2PCH_SPI_MOSI_2PCH_SPI_MISO
SPI_HOLD2#SPI_WP2#
PCH_SPI_CS0#_
PCH_SPI_CLK_2PCH_SPI_MOSI_2PCH_SPI_MISO_
SPI_WP2#SPI_HOLD2#
PCH_SPI_CLK_
PCH_SPI_VCC
PCH_SPKR <42>
HDA_SDIN <42>
SERIRQ
<40> LPC_AD0 SATA_PRX_DTX_N0 <34>SATA_PRX_DTX_P0 <34>SATA_PTX_DRX_N0 <34>SATA_PTX_DRX_P0 <34>
<40> LPC_AD
<40> LPC_AD
<40> LPC_AD
<40> LPC_FRAME#
<40>
HDA_SYNC_AUDIO <42>
HDA_SDOUT_AUDIO <42>
HDA_RST_AUDIO# <42>
HDA_BITCLK_AUDIO <42>
PCH_SATALED#
<41>
ME_EN <40>
SATA_PRX_DTX_N1 <37>SATA_PRX_DTX_P1 <37>SATA_PTX_DRX_N1 <37>SATA_PTX_DRX_P1 <37>SATA_PRX_DTX_N2 <34>SATA_PRX_DTX_P2 <34>SATA_PTX_DRX_N2 <34>SATA_PTX_DRX_P2 <34>
+RTCVCC
+RTCVCC
+1.05VS_VTT+1.05VS_VTT
+3VS
+3VALW_PCH
+3VALW_PCH
+3VS
+CHGRTC +RTCVCC
+RTCBATT
+3VS
+3VS
+3VS
+RTCBATT
+3VS
+3VS
+3VS
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
13
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
13
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
13
Friday, January 06, 2012
Compal Electronics, Inc.
RTCRST close RAM door SRTCRST close RAM door
HDD
H
H
Integrated VRM enable
L
L
**INTVRMENIntegrated VRM disable
HIGH= Enable ( No Reboot ) LOW= Disable (Default)
***^
*(INTVRMEN should always be pull high.)ME debug mode,this signal has a weak internal PDLow = Disabled (Default)High = Enabled [Flash Descriptor Security Overide]This signal has a weak internal pull-downOn Die PLL VR Select is supplied by1.5V when smapled high 1.8V when sampled lowNeeds to be pulled High for Huron River platfrom HDA_SDO
as Capella
ME
override
(GPIO33)
Boot
BIOS
GPIO
01
- SPI
GPIO
LPCReserved
Boot
BIOS
Strap^1
1
0
010
ODD
20mil
20mil
This
part
had
been
re-modified
be^
careful,if
link
symbol!!
SPI ROM FOR ME (4MB)Footprint 200mil
Rserve the 2M ROM for Win
GPIO
01
Switchable*
GPU
Non-Switchable
SGEN#
Prevent back drive issue.
MSATA
Modify
R
R
Modify
Modify
R Co-lay
NPCE885N
R04 modify
R04 modify
Modify
R Delete
Co-lay
NPCE885N
SCHEMATIC,MB A
4019ID
60
B
R375R3751K_0402_5%1K_0402_5% 2 1
R
33_0402_5%
R
33_0402_5%
1
2 T75 @ PAD
T75 @ PAD R
33_0402_5% WIN8@ R
33_0402_5% WIN8@ 1
2
C
1U_0603_10V6K
C
1U_0603_10V6K
1 2
T76 @ PAD
T76 @ PAD JCMOS1SHORT PADSJCMOS1SHORT PADS 1 @@ 2
C @33P_0402_50V8K C @33P_0402_50V8K
C 15P_0402_50V8J
C 15P_0402_50V8J
1 2
1 C686C68615P_0402_50V8J15P_0402_50V8J 2
U42 MX25L1606EM2I-12G_SO
WIN8@ U42 MX25L1606EM2I-12G_SO
WIN8@ CS# 1
SO^
2
WP# 3
GND 4
VCC
(^8)
HOLD# 7
SCLK
(^6 5) SI
R792R7921M_0402_5%1M_0402_5% 1 2
R
20K_0402_1% R
1 20K_0402_1%
2
R
1K_0402_5%
R
1K_0402_5% 1
2
JBATT1 SUYIN_060003HA002G202ZL
CONN@
JBATT1 SUYIN_060003HA002G202ZL
CONN@
1 + - 2
R 37.4_0402_1%
R 37.4_0402_1%^1
2
R
[email protected]_0402_5% R
WIN8@ 1 3.3K_0402_5%
2
R
[email protected]_0402_5%
R
WIN8@ 1 3.3K_0402_5%
2
R259R25910K_0402_5%10K_0402_5% 1 2
R241R24149.9_0402_1%49.9_0402_1% 1
2
R
33_0402_5% WIN8@ R
33_0402_5% WIN8@ 1 2
R
10K_0402_5%
R
10K_0402_5% 1
2 R
4.7K_0402_5%
R
4.7K_0402_5%
1
2
R
3.3K_0402_5%
R
3.3K_0402_5%
1
2
R 33_0402_5%
R 33_0402_5%^1
2
C @33P_0402_50V8K C @33P_0402_50V8K
1 C471C4710.1U_0402_16V4Z0.1U_0402_16V4Z 2
R
10M_0402_5% R
10M_0402_5% 1
2
R
20K_0402_1% R
1 20K_0402_1%
2
R
33_0402_5%
R
33_0402_5%
1
2 T77 @ PAD
T77 @ PAD
R
1K_0402_5% @
R
1K_0402_5% @ 1
2
R544R54433_0402_5%33_0402_5% 1
2
Y
Y
32.768KHZ_12.5PF_9H
Y
32.768KHZ_12.5PF_9H
1
2
R204822_0402_5% @^
R204822_0402_5% @^
2
R674@ R674@51_0402_5%51_0402_5%
1
2
R 0_0402_5%
R 0_0402_5%
1
2
R
33_0402_5% WIN8@ R
33_0402_5% WIN8@ 1 2
R625R625750_0402_1%750_0402_1% 1
2
R
330K_0402_5%
R
330K_0402_5%
1
2
R 1K_0402_5%@
R 1K_0402_5%@
1
2
R
1M_0402_5%
R
1M_0402_5%
1
2
1 @@R540R5400_0402_5%0_0402_5%
2
RTC IHDA
LPC SATA
JTAG^ SPI
6G SATA
U33A COUGARPOINT_FCBGA989~DHM65@SA00004EEY
RTC IHDA
LPC SATA
JTAG^ SPI
6G SATA
U33ARTCX1 COUGARPOINT_FCBGA989~DHM65@SA00004EEY
A
RTCX C
INTVRMEN C
INTRUDER# K
HDA_BCLK N
HDA_SYNC L
HDA_RST# K
HDA_SDIN
E
E
HDA_SDIN G
HDA_SDIN C
HDA_SDO A
SATALED#
P
P
FWH0 / LAD
C
FWH1 / LAD
A
FWH2 / LAD
B
FWH3 / LAD
C
LDRQ1# / GPIO
K
FWH4 / LFRAME#
D
LDRQ0#
E
RTCRST# D
HDA_SDIN A
HDA_DOCK_EN# / GPIO C
HDA_DOCK_RST# / GPIO N
SRTCRST# G
SATA0RXN
AM
AM
SATA0RXP
AM
SATA0TXN
AP
SATA0TXP
AP
SATA1RXN
AM
SATA1RXP
AM
SATA1TXN
AP
SATA1TXP
AP
SATA2RXN
AD
SATA2RXP
AD
SATA2TXN
AH
SATA2TXP
AH
SATA3RXN
AB
SATA3RXP
AB
SATA3TXN
AF
AF
SATA3TXP
AF
SATA4RXN
Y
SATA4RXP
Y
SATA4TXN
AD
SATA4TXP
AD
SATA5RXN
Y
SATA5RXP
Y
SATA5TXN
AB
SATA5TXP
AB
SATAICOMPI
Y
SPI_CLK T
SPI_CS0# Y
SPI_CS1# T
SPI_MOSI V
SPI_MISO
U
U
SATA0GP / GPIO
V
SATA1GP / GPIO
P
JTAG_TCK J
JTAG_TMS H
JTAG_TDI K
JTAG_TDO H
SERIRQ
V
SPKR T
SATAICOMPO
Y
SATA3COMPI
AB
SATA3RCOMPO
AB
SATA3RBIAS
AH
U36U36 1 CS# 32M W25Q32BVSSIG_SO832M W25Q32BVSSIG_SO
SO/SIO
(^2)
WP# 3
GND 4
VCC
(^8)
HOLD# 7
SCLK
(^6)
SI/SIO
(^5)
R
10K_0402_5%
R
10K_0402_5% 1
2
G
D S
Q36S TR SSM3K7002F 1N SC59- G
D S
Q36S TR SSM3K7002F 1N SC59- 2
1 3
U33U33 BD82HM77 QPRG C1 BGA 989PBD82HM77 QPRG C1 BGA 989PHM77@HM77@SA00005AGE0SA00005AGE
R545R54533_0402_5%33_0402_5% 1
2
R258R25810K_0402_5%10K_0402_5%@@ 1 2
C 1U_0603_10V6K
C 1U_0603_10V6K
1 2
JME1SHORT PADSJME1SHORT PADS 1 2 @@
R866R866 1 @@22_0402_5%22_0402_5%
2
D13D13 CHN202UPT_SC70-3CHN202UPT_SC70-
1 2
3
R
3.3K_0402_5%
R
3.3K_0402_5%
1
2
R
33_0402_5%
R
33_0402_5%
1
2
R555R55533_0402_5%33_0402_5% 1
2
5 5
4 4
3 3
2 2
1 1
PCH_GPIO11PCH_SMBCLKPCH_SMBDATA PCH_SML1CLKPCH_SML1DATA CLK_CPU_DMI#CLK_CPU_DMI CLK_PCI_LPBACKXTAL25_INXTAL25_OUTXCLK_RCOMP
PCH_GPIO PCIE_PRX_DTX_N1PCIE_PRX_DTX_P1PCIE_PTX_DRX_N1PCIE_PTX_DRX_P1PCIE_PRX_DTX_N2PCIE_PRX_DTX_P2PCIE_PTX_DRX_N2PCIE_PTX_DRX_P
CLK_PCI_LPBACK
MINI1_CLKREQ# PCH_GPIO
XTAL25_INXTAL25_OUT
RST_GATE CLK_FLEX
MINI1_CLKREQ#USB30_CLKREQ#LAN_CLKREQ#MINI2_CLKREQ#PCH_GPIO44PCH_GPIO45PCH_GPIO
PCH_SML1DATAPCH_SML1CLK
EC_SMB_DA2EC_SMB_CK
CLKIN_GND1#CLKIN_GND
PCH_GPIO
PCH_GPIO73 LAN_CLKREQ# PEG_CLKREQ#_R
PCH_GPIO
PCH_GPIO11RST_GATEPCH_SMBCLKPCH_SMBDATAPCH_SML1CLKPCH_SML1DATAPCH_GPIO
USB30_CLKREQ#
PCH_GPIO
PCH_GPIO
DGPU_PRSNT#
D_CK_SDATAD_CK_SCLK
PCH_SMBDATAPCH_SMBCLK
CLK_BUF_CPU_DMI#CLK_BUF_CPU_DMICLK_BUF_DREF_96M#CLK_BUF_DREF_96MCLK_BUF_PCIE_SATA#CLK_BUF_PCIE_SATACLK_BUF_ICH_14M
CLK_PCIE_LAN#CLK_PCIE_LAN CLK_PEG_VGA#CLK_PEG_VGA
DGPU_PRSNT#
CLK_PCIE_MINI1#CLK_PCIE_MINI
CLK_FLEX
PCH_GPIO
CLK_CPU_DPLL#CLK_CPU_DPLL CLK_FLEX
PEG_CLKREQ#_R MINI2_CLKREQ#
CLK_CPU_DMI#
<5>
CLK_CPU_DMI
<5>
PCIE_PRX_DTX_N <35>
PCIE_PTX_C_DRX_N <35>
PCIE_PRX_DTX_P <35>
PCIE_PTX_C_DRX_P <35>
PCIE_PRX_DTX_N <37>
PCIE_PRX_DTX_P <37>
PCIE_PTX_C_DRX_N <37>
PCIE_PTX_C_DRX_P <37>
CLK_PCIE_MINI1# <37>
CLK_PCIE_MINI <37>
MINI1_CLKREQ# <37>
CLK_PCI_LPBACK
<17>
PCH_SMBCLK
<37>
PCH_SMBDATA
<37>
RST_GATE
<6,11,12>
EC_SMB_CK
<22,40>
EC_SMB_DA
<22,40>
CLK_PCIE_LAN# <35>
CLK_PCIE_LAN <35>
LAN_CLKREQ# <35>
CLK_PEG_VGA# <22>
CLK_PEG_VGA <22>
D_CK_SDATA
<11,12,41>
D_CK_SCLK
<11,12,41>
CLK_CPU_DPLL#
<5>
CLK_CPU_DPLL
<5>
PEG_CLKREQ# <22>
VGA_ON
<17,25,44,51,53>
+1.05VS_VTT
+3VS +3VALW_PCH
+3VS
+3VALW_PCH
+3VS
+3VS
+3VS +3VS
+3VALW_PCH
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
14
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
14
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
14
Friday, January 06, 2012
Compal Electronics, Inc.
PCIE LAN
Mini Card 1 (WLAN)
Reserve
for
EMI
please
close
to
U
Mini Card 1(WLAN)
PCIE LAN
Pull down 10K ohmfor using internal Clock
For DDR Pull up at EC side.For VGA,EC
GPIO67^01
DIS,OPTIMUS
UMA
DGPU_PRSNT#
120
MHz
for
eDP
Pull
high @ VGA side
for
R02 Modify^ safe
R
modify
SCHEMATIC,MB A
4019ID
60
B
R
10K_0402_5%
R
10K_0402_5%
1
2
R
2.2K_0402_5%
R
2.2K_0402_5%
1
2
Q38B
DMN66D0LDW-7_SOT363-
Q38B
DMN66D0LDW-7_SOT363-
3
4 5
R
10K_0402_5%
R
10K_0402_5% 1
2
R669R6694.7K_0402_5%4.7K_0402_5% 1
2
R
10K_0402_5%
R
10K_0402_5% 1
2
2 DIS@DIS@R160R16010K_0402_5%10K_0402_5% 1
T
PAD
@^
T
PAD
@
R
10K_0402_5%
R
10K_0402_5%
1
2
R
2.2K_0402_5%
R
2.2K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
R 10K_0402_5%
R 10K_0402_5%
1 2
G
D S Q
2N7002H_SOT23-
DIS@
G
D S Q
2N7002H_SOT23-
DIS@
2
1 3
T
PAD
@^
T
PAD
@
R
10K_0402_5%
R
10K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
C
.1U_0402_16V7K
C
.1U_0402_16V7K 1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
C 10P_0402_50V8J
C 10P_0402_50V8J
1 2
R
10K_0402_5%
R
10K_0402_5% 1
2 R
10K_0402_5% @
R
10K_0402_5% @^
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
Y^
25MHZ 10PF 7V Y^
25MHZ 10PF 7V
GND^2
3 3
1
1
GND^4
R526R52690.9_0402_1%90.9_0402_1% 1
2
C
.1U_0402_16V7K
C
.1U_0402_16V7K 1
2
Q38A
DMN66D0LDW-7_SOT363-
Q38A
DMN66D0LDW-7_SOT363-
6
1 2
T^
PAD
@^
T^
PAD
@
R
10K_0402_5%
R
10K_0402_5% 1
2 R
10K_0402_5%
R
10K_0402_5% 1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
1K_0402_5%
R
1K_0402_5% 1
2
C
.1U_0402_16V7K
C
.1U_0402_16V7K 1
2
R530@R530@33_0402_5%33_0402_5%
1
2
R 2.2K_0402_5%
@R
2.2K_0402_5%
@
1 2
R
10K_0402_5%
R
10K_0402_5% 1
2
R 2.2K_0402_5%
@R
2.2K_0402_5%
@
1 2
R670R6704.7K_0402_5%4.7K_0402_5% 1
2
Q40B
DMN66D0LDW-7_SOT363-
Q40B
DMN66D0LDW-7_SOT363-
3
4 5
1 UMAO@UMAO@R159R15910K_0402_5%10K_0402_5% 2
R DIS@0_0402_5% R DIS@0_0402_5%
1 2
R
10K_0402_5%
R
10K_0402_5%
1
2
R 10K_0402_5%
DIS@R 10K_0402_5%
DIS@
1 2
PCI-E*
CLOCKS
CLOCKS FLEX
SMBUS Controller
Link
U33B COUGARPOINT_FCBGA989~DHM65@
PCI-E*
CLOCKS
CLOCKS FLEX
SMBUS Controller
Link
U33BPERN1 COUGARPOINT_FCBGA989~DHM65@ BG
PERP BJ
PERN BE
PERP BF
PERN BG
PERP BJ
PERN BF
PERP BE
PERN BG
PERP BH
PERN BJ
PERP BG
PERN BG
PERP BJ
PERN BE
PERP BC
PETN AV
PETP AU
PETN BB
PETP AY
PETN AV
PETP AU
PETN AY
PETP BB
PETN AY
PETP BB
PETN AU
PETP AV
PETN AY
PETP BB
PETN AW
PETP AY
CLKOUT_PCIE0N Y
CLKOUT_PCIE0P Y
CLKOUT_PCIE1N AB
CLKOUT_PCIE1P AB
CLKOUT_PCIE2N AA
CLKOUT_PCIE2P AA
CLKOUT_PCIE3N Y
CLKOUT_PCIE3P Y
CLKOUT_PCIE4N Y
CLKOUT_PCIE4P Y
CLKOUT_PCIE5N V
CLKOUT_PCIE5P V
CLKIN_DMI2_N
BJ
CLKIN_DMI2_P
BG
CLKIN_DMI_N
BF
CLKIN_DMI_P
BE
CLKIN_DOT_96N
G
CLKIN_DOT_96P
E
CLKIN_SATA_N / CKSSCD_N
AK
CLKIN_SATA_P / CKSSCD_P
AK
XTAL25_IN
V
XTAL25_OUT
V
REFCLK14IN
K
CLKIN_PCILOOPBACK
H
CLKOUT_PEG_A_N
AB
CLKOUT_PEG_A_P
AB
PEG_A_CLKRQ# / GPIO
M
PCIECLKRQ0# / GPIO J
PCIECLKRQ1# / GPIO M
PCIECLKRQ2# / GPIO V
PCIECLKRQ3# / GPIO A
PCIECLKRQ4# / GPIO
L
PCIECLKRQ5# / GPIO L
CLKOUTFLEX0 / GPIO
K
CLKOUTFLEX1 / GPIO
F
CLKOUTFLEX2 / GPIO
H
CLKOUTFLEX3 / GPIO
K
CLKOUT_DMI_N
AV
CLKOUT_DMI_P
AU
PEG_B_CLKRQ# / GPIO E
CLKOUT_PEG_B_P AB
CLKOUT_PEG_B_N AB
XCLK_RCOMP
Y
CLKOUT_DP_P / CLKOUT_BCLK1_P
AM
CLKOUT_DP_N / CLKOUT_BCLK1_N
AM
CLKOUT_PCIE6N V
CLKOUT_PCIE6P V
PCIECLKRQ7# / GPIO K
CLKOUT_PCIE7N V
CLKOUT_PCIE7P V
CLKOUT_BCLK0_N / CLKOUT_PCIE8N AK
CLKOUT_BCLK0_P / CLKOUT_PCIE8P AK
SMBALERT# / GPIO
E
SMBCLK
H
SMBDATA
C
SML0ALERT# / GPIO
A
SML0CLK
C
SML0DATA
G
SML1ALERT# / PCHHOT# / GPIO
C
SML1CLK / GPIO
E
SML1DATA / GPIO
M
CL_CLK
M
CL_DATA
T
CL_RST1#
P
PCIECLKRQ6# / GPIO T
Q40A
DMN66D0LDW-7_SOT363-
Q40A
DMN66D0LDW-7_SOT363-
6
1 2
C @C642@22P_0402_50V8J22P_0402_50V8J 1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
1 C631C63110P_0402_50V8J10P_0402_50V8J 2
R
2.2K_0402_5%
R
2.2K_0402_5%
1
2
R
1M_0402_5%
R
1M_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5% 1
2
R
2.2K_0402_5%
R
2.2K_0402_5%
1
2
C
.1U_0402_16V7K
C
.1U_0402_16V7K 1
2
5 5
4 4
3 3
2 2
1 1
SDVO_SCLKSDVO_SDATAPCH_DPB_HPD
PCH_TXCLK-PCH_TXCLK+PCH_TXOUT0-PCH_TXOUT1-PCH_TXOUT2-PCH_TXOUT0+PCH_TXOUT1+PCH_TXOUT2+ PCH_CRT_BPCH_CRT_GPCH_CRT_RPCH_CRT_CLKPCH_CRT_DATA
CRT_IREF
IGPU_BKLT_EN
PCH_CRT_BPCH_CRT_GPCH_CRT_R
CTRL_CLKCTRL_DATALVDS_IBGLVD_VREF
PCH_DPB_N0PCH_DPB_P0PCH_DPB_N1PCH_DPB_P1PCH_DPB_N2PCH_DPB_P2PCH_DPB_N3PCH_DPB_P
CTRL_CLKCTRL_DATAPCH_LCD_CLKPCH_LCD_DATA PCH_CRT_CLKPCH_CRT_DATA
ENBKL
IGPU_BKLT_ENIGPU_BKLT_EN PCH_DPB_HPD
SDVO_SCLK
<33>
SDVO_SDATA
<33>
PCH_DPB_HPD
<33>
PCH_TXCLK- <31>
PCH_TXCLK+ <31>
PCH_TXOUT0- <31>
PCH_TXOUT1- <31>
PCH_TXOUT2- <31>
PCH_TXOUT0+ <31>
PCH_TXOUT1+ <31>
PCH_TXOUT2+ <31> PCH_CRT_DATA <32>
PCH_CRT_R <32>
PCH_CRT_G <32>
PCH_CRT_B <32>
PCH_ENVDD <31>
DPST_PWM <31>
PCH_LCD_DATA <31>
PCH_CRT_CLK <32>
PCH_DPB_N
<33>
PCH_DPB_N
<33>
PCH_DPB_P
<33>
PCH_DPB_P
<33>
PCH_DPB_N
<33>
PCH_DPB_P
<33>
PCH_DPB_N
<33>
PCH_DPB_P
<33>
ENBKL <40>
PCH_LCD_CLK <31>
PCH_CRT_VSYNC <32>
PCH_CRT_HSYNC <32>
+3VS +3VS
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
16
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
16
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
16
Friday, January 06, 2012
Compal Electronics, Inc.
Pull high at LVDS conn side.
HDMI D2HDMI D1HDMI D0HDMI CLK
SDVO_CTRLDATA strap pull highat level shift page
RF
request
R
Modify
SCHEMATIC,MB A
4019ID
60
B
R177R1770_0402_5%0_0402_5%
1
2
R
2.2K_0402_5%
R
2.2K_0402_5%
1
2
C 10P_0402_50V8J
@ C 10P_0402_50V8J
@^
1 2
R
0_0402_5%
R
0_0402_5% 1
2
R
2.2K_0402_5%
R
2.2K_0402_5%
1
2
R
150_0402_1%
R
150_0402_1%
1
2
R
150_0402_1%
R
150_0402_1%
1
2
1 @@C2044C204410P_0402_50V8J10P_0402_50V8J 2
R
2.2K_0402_5%
R
2.2K_0402_5%
1
2
R
2.2K_0402_5%
R
2.2K_0402_5%
1
2
R
2.2K_0402_5%
R
2.2K_0402_5%
1
2
R 2.37K_0402_1%
R 2.37K_0402_1%
1
2
C
1U_0402_6.3V6K
C
1U_0402_6.3V6K
1
2
LVDS
Interface Display Digital CRT
U33D COUGARPOINT_FCBGA989~DHM65@
LVDS
Interface Display Digital CRT
U33D L_BKLTCTL COUGARPOINT_FCBGA989~DHM65@
P
L_BKLTEN J
L_CTRL_CLK T
L_CTRL_DATA P
L_DDC_CLK T
L_DDC_DATA K
L_VDD_EN M
LVDSA_CLK# AK
LVDSA_CLK AK
LVDSA_DATA# AN
LVDSA_DATA# AM
LVDSA_DATA# AK
LVDSA_DATA# AJ
LVDSA_DATA AN
LVDSA_DATA AM
LVDSA_DATA AK
LVDSA_DATA AJ
LVDSB_CLK#
AF
AF
LVDSB_CLK AF
LVDSB_DATA# AH
LVDSB_DATA# AH
LVDSB_DATA# AF
LVDSB_DATA# AF
LVDSB_DATA AH
DDPB_0N
AV
DDPB_1N
AV
LVD_VREFH AE
LVD_VREFL AE
DDPD_2N
BF
DDPD_3N
BJ
DDPB_2N
AU
DDPB_3N
AV
DDPC_0N
AY
DDPC_1N
AY
DDPC_2N
BA
DDPC_3N
BB
DDPD_0N
BB
DDPD_1N
BF
DDPB_0P
AV
DDPB_1P
AV
DDPD_2P
BE
DDPD_3P
BG
DDPB_2P
AU
DDPB_3P
AV
LVDSB_DATA AH
LVDSB_DATA AF
LVDSB_DATA AF
LVD_IBG AF
LVD_VBG AF
DDPC_1P
AY
DDPC_0P
AY
DDPC_2P
BA
DDPC_3P
BB
DDPD_0P
BB
DDPD_1P
BE
CRT_BLUE N
CRT_DDC_CLK T
CRT_DDC_DATA M
CRT_GREEN P
CRT_HSYNC M
CRT_IRTN T
CRT_RED T
CRT_VSYNC M
DAC_IREF T
SDVO_CTRLCLK
P
SDVO_CTRLDATA
M
DDPC_CTRLCLK
P
DDPC_CTRLDATA
P
DDPD_CTRLCLK
M
DDPD_CTRLDATA
M
DDPB_AUXN
AT
DDPC_AUXN
AP
DDPD_AUXN
AT
DDPB_AUXP
AT
DDPC_AUXP
AP
DDPD_AUXP
AT
DDPB_HPD
AT
DDPC_HPD
AT
DDPD_HPD
BH
SDVO_TVCLKINP
AP
SDVO_TVCLKINN
AP
SDVO_STALLP
AM
SDVO_STALLN
AM
SDVO_INTP
AP
SDVO_INTN
AP
R
150_0402_1%
R
150_0402_1%
1
2
R 1K_0402_0.5%
R 1K_0402_0.5%
1 2
R
2.2K_0402_5%
R
2.2K_0402_5%
1
2
5 5
4 4
3 3
2 2
1 1
USBRBIAS
PCI_PIRQA#PCI_PIRQB#PCI_PIRQC#PCI_PIRQD#PCH_GPIO52 PCH_GPIO
CLK_PCI0CLK_PCI1CLK_PCI2CLK_PCI3CLK_PCI
USB_OC0#USB_OC1#USB_OC2#USB_OC3#USB_OC4#USB_OC5#SMIBUSB_OC7#
DF_TVS
DF_TVS
PCH_GPIO
USB_OC0#USB_OC2#USB_OC7#USB_OC5# USB_OC4#USB_OC3#SMIB
USB20_N8USB20_P8USB20_N10USB20_P
PCI_PIRQA#PCI_PIRQD#PCI_PIRQC#PCI_PIRQB#PCH_GPIO55PCH_GPIO5PCH_GPIO2PCH_GPIO4PCH_GPIO
USB20_N1USB20_P
DGPU_HOLD_RST#VGA_ON
VGA_ON DGPU_HOLD_RST#
DGPU_HOLD_RST#
PCH_GPIO51PCH_GPIO
PCH_GPIO51 PCH_GPIO
PCH_GPIO
PCH_GPIO53PCH_GPIO
CLK_PCI_LPBACKCLK_PCI_LPC
USB_OC1#
PLT_RST#
PLT_RST#
PCH_GPIO PCH_USB3_RX1_NPCH_USB3_RX1_PPCH_USB3_TX1_NPCH_USB3_TX1_P
PLT_RST#
USB20_N2USB20_P
PLT_RST#PLTRST_VGA#PLTRST_VGA#
USB20_N0USB20_P0 USB20_N11USB20_P
PLT_RST_BUF#
H_SNB_IVB#^ <35,37,40>
<5>
PLTRST_VGA#
<22>
CLK_PCI_LPBACK <14>
CLK_PCI_LPC <40>
USB20_N
<37>
USB20_P
<37>
USB20_N
<31>
USB20_P
<31>
USB20_N
<39>
USB20_P
<39>
VGA_ON
<14,25,44,51,53>
PLT_RST# <5> PCH_USB3_TX1_P <39>
PCH_USB3_RX1_N <39>
PCH_USB3_RX1_P <39>
PCH_USB3_TX1_N <39>
USB20_N
<39>
USB20_P
<39>
SMIB
USB20_N
<39>
USB20_P
<39>
USB20_N
<39>
USB20_P
<39>
USB_OC0#
<39>
+3VS
+1.8VS
+3VALW_PCH
+3VS
+3VALW TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
17
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
17
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
17
Friday, January 06, 2012
Compal Electronics, Inc.
Set
to
Vcc
when
HIGH
DMI
Termination
Voltage
DF_TVS
Set
to
VSS
VSS
when
LOW
Within 500 mils
CLOSE
TO
THE
BRANCHING
POINT
Mini Card 1 (WLAN) CMOS Camera (LVDS)
Bit
Boot BIOSGNT1#/GPIO
Strap
bit
BBS
Bit 01 10
10 10
Boot BIOSDestinationReserved
PCISPILPC
Some PCH config not support USB port 6 & 7.
DG
CRB1.
PH
2.2K
series
1K
GPIO51 Internal pull
high
USB/B (Right side)
For
RF
request
USB Conn. Colay USB3.
R02 modify
for
ESD
R
modify
R
Modify
USB/B (Right side)
R
Modify
BlueTooth
R
Modify
SCHEMATIC,MB A
4019ID
60
B
R
22_0402_5%
R
22_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
U
MC74VHC1G08DFT2G_SC70-
DIS@
U
MC74VHC1G08DFT2G_SC70-
DIS@
IN 1
IN 2
OUT
(^4)
5 VCCGND 3
R
10K_0402_5%
R
10K_0402_5%
1
2
R
22_0402_5%
R
22_0402_5% 1
2
R
22.6_0402_1% R
22.6_0402_1% 1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
1 R633R6332.2K_0402_5%2.2K_0402_5% 2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
T PAD
@ T PAD
@
R DIS@100K_0402_5%
R 1 DIS@100K_0402_5% 2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
T PAD
@ T PAD
@
C
22P_0402_50V8J
C633^ @
22P_0402_50V8J
@
1 2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
10K_0402_5%
PUSB@
R
10K_0402_5%
PUSB@ 1
2
C63222P_0402_50V8J @
C63222P_0402_50V8J (^1) @ 2
R
1K_0402_5%
R
(^1) 1K_0402_5%
2
R
10K_0402_5%
R
10K_0402_5%
1
2
T PAD
@ T PAD
@
T PAD
@ T PAD
@
R
10K_0402_5%
R
10K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
8.2K_0402_5%
R
8.2K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
1 R297R297100K_0402_5%100K_0402_5% 2
R
10K_0402_5%
R
10K_0402_5%
1
2
C
0.1U_0402_16V4Z
C
0.1U_0402_16V4Z 1
2
RSVD
NVRAM PCI
USB
U33E COUGARPOINT_FCBGA989~DHM65@
RSVD
NVRAM PCI
USB
U33E COUGARPOINT_FCBGA989~DHM65@
NV_ALE
AV
NV_CE#
AY
NV_CE#
AV
NV_CE#
AU
NV_CE#
BG
NV_CLE
AY
NV_DQS
AT
NV_DQS
BC
NV_DQ0 / NV_IO
AU
NV_DQ1 / NV_IO
AT
NV_DQ10 / NV_IO
BB
NV_DQ11 / NV_IO
BB
NV_DQ12 / NV_IO
BB
NV_DQ13 / NV_IO
BE
NV_DQ14 / NV_IO
BD
NV_DQ15 / NV_IO
BF
NV_DQ2 / NV_IO
AT
NV_DQ3 / NV_IO
AT
NV_DQ4 / NV_IO
AY
NV_DQ5 / NV_IO
AT
NV_DQ6 / NV_IO
AV
NV_DQ7 / NV_IO
AV
NV_DQ8 / NV_IO
BB
NV_DQ9 / NV_IO
BA
NV_RB#
AT
NV_RCOMP
AV
NV_RE#_WRB
AY
NV_RE#_WRB
BA
NV_WE#_CK
AT
NV_WE#_CK
BF
PIRQA# K
PIRQB# K
PIRQC#
H
H
PIRQD# G
REQ1# / GPIO C
REQ2# / GPIO C
REQ3# / GPIO
E
E
GNT1# / GPIO D
GNT2# / GPIO E
GNT3# / GPIO F
PIRQE# / GPIO G
PIRQF# / GPIO G
PIRQG# / GPIO C
PIRQH# / GPIO D
USBP0N
C
USBP0P
A
USBP1N
C
USBP1P
B
USBP2N
C
USBP2P
A
USBP3N
K
USBP3P
H
USBP4N
E
USBP4P
D
USBP5N
C
USBP5P
A
USBP6N
C
USBP6P
B
USBP7N
N
USBP7P
M
USBP8N
L
USBP8P
K
USBP9N
G
USBP9P
E
USBP10N
C
USBP10P
A
USBP11N
L
USBP11P
K
USBP12N
G
USBP12P
E
USBP13N
C
USBP13P
A
PME# K
CLKOUT_PCI H
CLKOUT_PCI H
CLKOUT_PCI J
USBRBIAS#
C
USBRBIAS
B
OC0# / GPIO
A
OC1# / GPIO
K
OC2# / GPIO
B
OC3# / GPIO
C
OC4# / GPIO
L
OC5# / GPIO
A
OC6# / GPIO
D
OC7# / GPIO
C
CLKOUT_PCI H
CLKOUT_PCI K
PLTRST# C
TP BG
TP BJ
TP BH
TP
AH
TP AH
TP
AK
TP AK
TP
Y
TP K
TP L
TP AB
TP AB
TP B
TP M
TP AY
TP BE
TP BC
TP BE
TP BJ
TP BC
TP BE
TP BF
TP BG
TP AV
TP BB
TP AU
TP AY
TP AU
TP AY
TP AV
TP AW
TP BJ
TP BG
TP
AM
TP AM
TP AH
TP11H3 TP N
TP C
TP BG
C
0.1U_0402_16V4Z
C
0.1U_0402_16V4Z 1
2
R DIS@100_0402_1%
R DIS@100_0402_1% 1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
C
0.1U_0402_16V4Z
C
0.1U_0402_16V4Z 1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
10K_0402_5%
R
10K_0402_5%
1
2
R
8.2K_0402_5%
DIS@
R
8.2K_0402_5%
DIS@ 1
2
U
MC74VHC1G08DFT2G_SC70-
U
MC74VHC1G08DFT2G_SC70-
IN 1
IN 2
OUT
(^4)
5 VCCGND 3
5 5
4 4
3 3
2 2
1 1
+VCCAFDI_VRM
+1.05VS_VTT +VCCAPLLEXP
+VCCAFDI_VRM
+VCCA_LVDS +VCCTX_LVDS +VCCAFDI_VRM
+1.05VS_VCCAPLL_FDI
+VCCADAC
+1.5VS
+VCCAFDI_VRM
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
+3VS
+1.05VS_VTT
+1.8VS
+3VS
+3VS
+3VS
+3VS
+1.8VS
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
19
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
19
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
19
Friday, January 06, 2012
Compal Electronics, Inc.
VCCVRM = 160mA
detal
waiting
for
newest
spec
VCCVRM==>1.5V
FOR
MOBILE
VCCVRM==>1.8V
FOR
DESKTOP
0.1uH
inductor,
200mA
1700mA
1mA 1mA 40mA
3711mA
47mA 190mA 10mA
228mA
+VCCADAC
should
be
powered
up
during
S
system
state.Note
that
Thermal
Sensor
shares
the
same
power
supply
rail
with
DAC
HDA_SYNC
PH(PLL
=+1.5VS)
GPIO28On-Die VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI
PLL
Voltage
Regulator
H
On-Die
PLL
voltage
regulator
enable
place
near
AT
place
near
AB
VccDFTERM
should
PH
+1.8VS
or
+3VS
For
SPI
control
logi
Core
Well
I/O
Buffer
DMI
buffer
logic
Internal
PLL
and
VRM(+1.5VS)
I/O
Buffer
Voltage
DMI
Clock
Buffer
Voltage
Spread
Modulators
Power
Supply
Differential
Clock
Buffers
Power
Supply
Analog
power
supply
for
LVDS
(Mobile
Only)Analog
power
supply
for
LVDS
(Mobile
Only)
VccSSC
I/O
Buffer
Voltage
V^
Internal
PLL
and
VRMs
V^
for
Desktop)
VccDIFFCLKN
PCH Power Rail Table
Processor
I/F
PCH
Core
Well
Reference
Voltage
Suspend
Well
Reference
Voltag
V_PROC_IOV5REFV5REF_SusVcc3_3VccADACVccADPLLAVccADPLLB
Display
DAC
Analog
Power.
This
power
is
supplied
by
the
core
well.
Voltage
Rail
VccCoreVccDMI
1.05^5 3.
Voltage
S
IccmaxCurrent(A)
Display
PLL
A^
power
VccIO
VccASW
VccSPI
VccDSW
VccpNAND
VccRTC
6 uA
VccSus3_
/^
VccSusHDA
VccVRM
/^
VccCLKDMI VccALVDS
VccTX_LVDS
Display
PLL
B
power
Internal
Logic
Voltage
DMI
Buffer
Voltage
Core
Well
I/O
buffers
V^
Supply
for
Intel
R^
Management
Engine
and
Integrated
LAN
V^
Supply
for
SPI
Controller
Logic
3.3v
supply
for
Deep
S4/S
well
1.8V
power
supply
for
DF_TVS
Battery
Voltage
Suspend
Well
I/O
Buffer
Voltage
High
Definition
Audio
Controller
Suspend
Voltage
On-Die VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2,VCCAPLLSATA
PLL
Voltage Regulator
H^
On-Die
PLL
voltage
regulator
enable
Trace 20mil
R
Modify
R
Modify
R
Modify
R
Modify
SCHEMATIC,MB A
4019ID
60
B
T PAD
@ T PAD
@
POWER CORE^ VCC
DMI VCCIO
CRT LVDS FDI
HVCMOS SPI / NAND
U33G COUGARPOINT_FCBGA989~DHM65@
POWER CORE^ VCC
DMI VCCIO
CRT LVDS FDI
HVCMOS SPI / NAND
U33GVCCCORE[1] COUGARPOINT_FCBGA989~DHM65@ AA
VCCCORE[2]
AC
AC
VCCCORE[3] AD
VCCCORE[4] AD
VCCCORE[5] AF
VCCCORE[6] AF
VCCCORE[7]
AG
AG
VCCCORE[8] AG
VCCCORE[9] AG
VCCCORE[10] AG
VCCCORE[11] AG
VCCCORE[12] AG
VCCCORE[13] AJ
VCCCORE[14] AJ
VCCCORE[15] AJ
VCCPNAND[4]
AJ
VCCPNAND[3]
AJ
VCCIO[17] AN
VCCIO[18] AN
VCCIO[19] AN
VCCIO[20] AP
VCCIO[23] AP
VCCIO[24] AT
VCCIO[15] AN
VCCIO[16] AN
VCCIO[21] AP
VCCIO[22] AP
VCCADAC
U
VCCTX_LVDS[1]
AM
VCCTX_LVDS[2]
AM
VCCALVDS
AK
VCCVRM[3]
AT
VCCVRM[2] AP
VCCAPLLEXP BJ
VCCFDIPLL BG
VCCIO[28] AN
VCCTX_LVDS[4]
AP
VCCTX_LVDS[3]
AP
VSSADAC
U
VSSALVDS
AK
VCCIO[27] AP
VCC3_3[6]
V
VCC3_3[7]
V
VCC3_3[3] BH
VCCPNAND[2]
AG
VCCPNAND[1]
AG
VCCDMI[1]
AT
VCCIO[25] AN
VCCIO[26] AN
VCCCORE[16] AJ
VCCCORE[17] AJ
VCCSPI
V
VCCIO[1]
AB
VCCDMI[2] AU
C20630.01U_0402_16V7KC20630.01U_0402_16V7K 1 2
C644.1U_0402_16V7KC644.1U_0402_16V7K 1 2
C347C3471U_0402_6.3V6K1U_0402_6.3V6K 1 2
1 C2064C206422U_0805_6.3V6M22U_0805_6.3V6M 2
C3201U_0402_6.3V6KC3201U_0402_6.3V6K 1 2
C703C7031U_0402_6.3V6K1U_0402_6.3V6K 1 2
C31410U_0603_6.3V6MC31410U_0603_6.3V6M 1 2
L
4.7UH_LQM18FN4R7M00D_20%
L 4.7UH_LQM18FN4R7M00D_20%
1
2
T PAD
@ T PAD
C353 @ 1U_0402_6.3V6KC3531U_0402_6.3V6K 1 2
C3251U_0402_6.3V6KC3251U_0402_6.3V6K 1 2
1 C305C3050.01U_0402_16V7K0.01U_0402_16V7K 2
1 C344C3441U_0402_6.3V6K1U_0402_6.3V6K 2
1 C308C3081U_0402_6.3V6K1U_0402_6.3V6K 2
L
0.1UH_MLF1608DR10KT_10%_
L
0.1UH_MLF1608DR10KT_10%_
1
2
C313C313.1U_0402_16V7K.1U_0402_16V7K 1 2
C3321U_0402_6.3V6KC3321U_0402_6.3V6K 1 2
C33410U_0603_6.3V6MC33410U_0603_6.3V6M 1 2
C3421U_0402_6.3V6KC3421U_0402_6.3V6K 1 2
1 C300C30022U_0805_6.3V6M22U_0805_6.3V6M 2
1 C322C322.1U_0402_16V7K.1U_0402_16V7K 2
R
0_0603_5%
R
0_0603_5% 1
2
C3461U_0402_6.3V6KC3461U_0402_6.3V6K 1 2
C6400.01U_0402_16V7KC6400.01U_0402_16V7K 1 2
1 C310C3100.01U_0402_16V7K0.01U_0402_16V7K 2
C349C349.1U_0402_16V7K.1U_0402_16V7K 1 2
C62910U_0603_6.3V6MC62910U_0603_6.3V6M 1 2
C3191U_0402_6.3V6KC3191U_0402_6.3V6K 1 2
R 0_0603_5%
R 0_0603_5% 1
2
5 5
4 4
3 3
2 2
1 1
+PCH_V5REF_SUS+VCCA_USBSUS+PCH_V5REF_RUN+3V_VCCPSUS +VCCAFDI_VRM
+3VS_VCC_CLKF
+3VS_VCC_CLKF33+VCCSUS +VCCRTCEXT
+VCCSST
+VCCAFDI_VRM+1.05VS_VCCA_A_DPL+1.05VS_VCCA_B_DPL +1.05VM_VCCSUS
+VCCSATAPLL
+VCCAPLL_CPY_PCH
+PCH_V5REF_SUS +PCH_V5REF_RUN
+PCH_VCCDSW
+1.05VS_VCCA_A_DPL+1.05VS_VCCA_B_DPL
PCH_PWR_EN#
PCH_PWR_EN# <35,44>
+3VS
+5VS
+3VALW_PCH
+5VALW_PCH
+1.05VS_VTT +1.05VS_VTT +1.05VS_VTT +3VALW_PCH
+1.05VS_VTT
+3VALW_PCH
+3VALW_PCH
+3VS
+1.05VS_VTT +1.05VS_VTT
+RTCVCC
+VCCAFDI_VRM
+1.05VS_VTT
+1.05VS_VTT
+3VALW_PCH
+3VALW_PCH
+3VS
+1.05VS_VTT
+1.05VS_VTT
+5VALW_PCH
+5VALW TitleSize^
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
20
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
20
Friday, January 06, 2012
Compal Electronics, Inc.
TitleSize
Document Number
Rev
Date:
Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
Custom
20
Friday, January 06, 2012
Compal Electronics, Inc.
Have internal VRM
1mA
95mA
1mA
903mA
1mA
80mA80mA 55mA130mA 1mA
10mA
Placenear AF33,AF34,AG34^ Placenear BJ
Placenear
AF
Placenear AG
suppied by internal1.05V VR Must NC
Place
near
P
Place
near
P
Place
near
AJ
Place
near
T
Place
near
AA16,W
Need Close P
+3VALW
and
0.1U
close
PCH
Not support Deep S4,S5connect to +3VALW
GPIO28On-Die PLL Voltage VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2,VCCAPLLSATA
Regulator
H
On-Die
PLL
voltage
regulator
enable
suppied by internal1.05V VR must NC
GPIO28On-Die VCCFDIPLL,VCCAPLLEXP,VCCAPLLDMI2,VCCAPLLSATA
PLL
Voltage
Regulator
H^
On-Die
PLL
voltage
regulator
enable
suppied
by
internal
1.05V
VR
Must
NC
VCC3_3 = 266mA detal waiting for newest specVCCDMI = 42mA detal waiting for newest spec
SGA00001700220U
2.5V M B
ESR
35mohm@100Khz
+5VALW TO +5VALW_PCH(PCH AUX Power)
R
Modify R^
Modify
R^
Modify
R02 Modify
R
Modify
R
Modify
R02 Modify
R
Modify
SCHEMATIC,MB A
4019ID
60
B
C3161U_0402_6.3V6KC3161U_0402_6.3V6K 1 2
C350C3501U_0402_6.3V6K1U_0402_6.3V6K 1 2
C311C311 1 1U_0402_6.3V6K1U_0402_6.3V6K 2
T PAD
@ T PAD
@
1 C244C2441U_0603_10V6K1U_0603_10V6K 2
C33522U_0805_6.3V6MC33522U_0805_6.3V6M 1 2
L
10UH_LB2012T100MR_20%
L
10UH_LB2012T100MR_20%
1
2
1 C315C3150.1U_0402_16V4Z0.1U_0402_16V4Z 2
C312C312 1 1U_0402_6.3V6K1U_0402_6.3V6K 2
C7004.7U_0603_6.3V6KC7004.7U_0603_6.3V6K 1 2
T
PAD @ T
PAD @
C3261U_0402_6.3V6KC3261U_0402_6.3V6K 1 2
T PAD
@ T PAD
@
C317C317 1 1U_0402_6.3V6K1U_0402_6.3V6K 2
1 C318C3180.1U_0603_25V7K0.1U_0603_25V7K 2
C27710U_0603_6.3V6MC27710U_0603_6.3V6M 1 2
C694.1U_0402_16V7KC694.1U_0402_16V7K T15 1 2 PAD
@ T PAD
@
C321C3211U_0402_6.3V6K1U_0402_6.3V6K 1 2
C687.1U_0402_16V7KC687.1U_0402_16V7K 1 2
1 C330C330.1U_0402_16V7K.1U_0402_16V7K 2
2 @@ R2090R2090 20K_0402_1%20K_0402_1% 1
L
10UH_LB2012T100MR_20%
L
10UH_LB2012T100MR_20%
1
2
C
.1U_0402_16V7K
C
.1U_0402_16V7K
1 2
C3041U_0402_6.3V6KC3041U_0402_6.3V6K 1 2
C340C340.1U_0402_16V7K.1U_0402_16V7K 1 2
D G S
Q2006AO3413L_SOT23-
@ D G S
Q2006AO3413L_SOT23-
@ 1 2 3
2 D7D7CH751H-40PT_SOD323-2CH751H-40PT_SOD323-2 1
1 C351C3511U_0402_6.3V6K1U_0402_6.3V6K 2
C2951U_0402_6.3V6KC2951U_0402_6.3V6K 1 2
L 10UH_LB2012T100MR_20%
L 10UH_LB2012T100MR_20%
1
2
C .1U_0402_16V7K
C .1U_0402_16V7K 1
2
1 C352C3521U_0402_6.3V6K1U_0402_6.3V6K 2
1 C704C704.1U_0402_16V7K.1U_0402_16V7K 2
C685.1U_0402_16V7KC685.1U_0402_16V7K 1 2
T PAD
@ T PAD
@
C33622U_0805_6.3V6MC33622U_0805_6.3V6M 1 2
R808R8080_0603_5%0_0603_5%@@ 2 1
1 C343C343.1U_0402_16V7K.1U_0402_16V7K 2
@@ C2062C20620.1U_0402_16V4Z0.1U_0402_16V4Z 1 2
T
PAD @ T
PAD @
1 C333C333.1U_0402_16V7K.1U_0402_16V7K 2
POWER
USB SATA Clock and Miscellaneous
HDA CPU RTC
PCI/GPIO/LPC MISC
U33J COUGARPOINT_FCBGA989~DHM65@
POWER
USB SATA Clock and Miscellaneous
HDA CPU RTC
PCI/GPIO/LPC MISC
U33J DCPSUSBYP COUGARPOINT_FCBGA989~DHM65@ V
VCCASW[1] AA
VCCASW[2] AA
VCCASW[3] AA
VCCASW[5] AA
VCCASW[6] AA
VCCSUSHDA
P
VCCSUS3_3[6]
P
VCCIO[34]
T
VCCIO[4]
AD
VCCASW[7] AA
VCCASW[8] AC
VCCASW[9] AC
VCCASW[10] AC
VCCASW[11] AC
VCCASW[12] AD
V5REF
P
VCC3_3[4]
T
VCCRTC A
VCCSUS3_3[10]
V
VCCSUS3_3[9]
V
VCCSUS3_3[8]
T
VCCSUS3_3[7]
T
VCCIO[2]
AC
VCCADPLLB BF
VCCIO[8] AF
V5REF_SUS
M
VCCIO[3]
AC
DCPSUS[1] T
VCCIO[10] AG
VCCADPLLA BD
VCCVRM[4]
Y
VCCACLK AD
DCPRTC N
VCCASW[4] AA
VCCIO[9] AF
VCCIO[7] AF
DCPSST V
VCCIO[5]
AF
VCCASW[22]
T
VCCASW[23]
V
VCCASW[21]
T
VCC3_3[1]
AA
VCC3_3[8]
W
VCCSUS3_3[2]
N
VCCSUS3_3[3]
N
VCCSUS3_3[4]
P
VCCSUS3_3[5]
P
VCCIO[29]
N
VCCIO[30]
P
VCCIO[31]
P
VCCIO[32]
T
V_PROC_IO BJ
VCCIO[33]
T
VCCIO[11] AG
VCCASW[13] AD
VCCASW[14] W
VCCASW[15] W
VCCASW[16] W
VCCASW[17] W
VCCASW[18] W
VCCASW[19] W
VCCASW[20] W
VCCIO[6]
AF
VCCVRM[1]
AF
VCCIO[12]
AH
VCCIO[13]
AH
VCC3_3[2]
AJ
VCCAPLLSATA
AK
DCPSUS[3]
AL
VCCIO[14] AL
DCPSUS[4]
AN
VCCSUS3_3[1]
AN
VCCAPLLDMI BH
DCPSUS[2] V
VCCDSW3_ T
VCC3_3[5] T
2 D8D8CH751H-40PT_SOD323-2CH751H-40PT_SOD323-2 1
R 100_0402_1%
R 100_0402_1%
1 2
C693.1U_0402_16V7KC693.1U_0402_16V7K 1 2
R 100_0402_1%
R 100_0402_1%
1 2
C3271U_0402_6.3V6KC3271U_0402_6.3V6K 1 2
C278330U_D2_2V_Y
C278330U_D2_2V_Y 1 2
R197R1970_0603_5%0_0603_5% 1
2
1 C309C309.1U_0402_16V7K.1U_0402_16V7K 2
C3311U_0402_6.3V6KC3311U_0402_6.3V6K 1 2
C2961U_0402_6.3V6KC2961U_0402_6.3V6K 1 2
