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Version 7.
Introduction to the
Quartus®^ II Software
Introduction to the
Quartus
II
Software
Altera Corporation 101 Innovation Drive San Jose, CA 95134 (408) 544- www.altera.com
®®
ALTERA CORPORATION INTRODUCTION TO THE QUARTUS II S OFTWARE ■ III
Preface ............................................................................................................................................. ix
TABLE OF CONTENTS
TABLE OF CONTENTS
TABLE OF CONTENTS
- Chapter 1: Design Flow.................................................................................................................. Documentation Conventions xi
- Introduction.......................................................................................................................
- Graphical User Interface Design Flow
- EDA Tool Design Flow
- Design Methodologies and Planning
- Top-Down and Bottom-Up Design Methodologies
- Top-Down Incremental Compilation Flow
- Bottom-Up Incremental Compilation Flow
- Chapter 2: Command Line And Tcl Design Flows
- Introduction.....................................................................................................................
- Command-Line Executables
- Using Standard Command-Line Commands & Scripts
- Using Tcl Commands.....................................................................................................
- Creating Makefile Scripts
- Chapter 3: Design Entry...............................................................................................................
- Introduction.....................................................................................................................
- Creating a Project............................................................................................................
- Using Revisions................................................................................................
- Using Version-Compatible Databases...........................................................
- Converting MAX+PLUS II Projects...............................................................
- Creating a Design
- Using the Quartus II Block Editor
- Using the Quartus II Text Editor....................................................................
- Using the Quartus II Symbol Editor..............................................................
- Using Verilog HDL, VHDL and AHDL........................................................
- Using the State Machine Editor
- Using Altera Megafunctions.........................................................................................
- Using Intellectual Property (IP) Megafunctions..........................................
- Using the MegaWizard Plug-In Manager.....................................................
- Instantiating Megafunctions in the Quartus II Software............................
- Instantiation in Verilog HDL & VHDL...........................................
- Using the Port & Parameter Definition
- Inferring Megafunctions...................................................................
- Instantiating Megafunctions in EDA Tools
- Using the Black Box Methodology..................................................
- Instantiation by Inference
- Using the Clear Box Methodology
- Chapter 4: Constraint Entry
- Introduction.....................................................................................................................
- Using the Assignment Editor
- Using the Pin Planner
- The Settings Dialog Box................................................................................................. IV ■ INTRODUCTION TO THE QUARTUS II S OFTWARE A LTERA C ORPORATION
- Assigning Design Partitions..........................................................................................
- Assigning Design Partitions in the Project Navigator
- Assigning Design Partitions with the Design Partitions Window............
- Importing Assignments
- Verifying Pin Assignments............................................................................................
- Chapter 5: Synthesis
- Introduction.....................................................................................................................
- Using Quartus II Verilog HDL & VHDL Integrated Synthesis................................
- Using Other EDA Synthesis Tools................................................................................
- Controlling Analysis & Synthesis
- Using Compiler Directives and Attributes...................................................
- Using Quartus II Logic Options.....................................................................
- Using Quartus II Synthesis Netlist Optimization Options
- Using the Design Assistant to Check Design Reliability
- Analyzing Synthesis Results With the Netlist Viewers.............................................
- The RTL Viewer
- The State Machine Viewer
- The Technology Map Viewer..........................................................................
- Chapter 6: Place and Route..........................................................................................................
- Introduction.....................................................................................................................
- Performing a Full Incremental Compilation
- Analyzing Fitting Results
- Using the Messages Window to View Fitting Results
- Using the Report Window or Report File to View Fitting Results............
- Using the Chip Planner to Analyze Results
- Using the Design Assistant to Check Design Reliability............................
- Optimizing the Fit
- Using Location Assignments..........................................................................
- Setting Options that Control Place & Route................................................. - Setting Fitter Options - Setting Physical Synthesis Optimization Options - Setting Individual Logic Options that Affect Fitting....................
- Using the Resource Optimization Advisor
- Using the Design Space Explorer.................................................................
- Preserving Assignments through Back-Annotation................................................
- Chapter 7: Block-Based Design
- Introduction...................................................................................................................
- Quartus II Block-Based Design Flow.........................................................................
- Using LogicLock Regions
- Using LogicLock Regions in Top-Down Incremental Compilation Flows...........
- Exporting & Importing Partitions for Bottom-Up Design Flows - Methodology............................................................................................ Preparing the Top-Level Design for a Bottom-Up Incremental Compilation
- Exporting a Partition to be Used in a Top-Level Project...........................
- Importing a Lower-Level Partition Into the Top-Level Project ALTERA CORPORATION INTRODUCTION TO THE QUARTUS II S OFTWARE ■ V
- Chapter 8: Simulation.................................................................................................................
- Introduction...................................................................................................................
- Simulating Designs with EDA Tools - Specifying EDA Simulation Tool Settings - Generating Simulation Output Files - EDA Simulation Flow.................................................................................... - EDA Tool Functional Simulation Flow......................................... - NativeLink Simulation Flow.......................................................... - Manual Timing Simulation Flow - Simulation Libraries
- Quartus II Simulator Simulating Designs with the
- Creating Waveform Files...............................................................................
- Using the Simulator Tool
- Chapter 9: Timing Analysis.......................................................................................................
- Introduction...................................................................................................................
- Choosing the TimeQuest or Classic Timing Analyzer
- TimeQuest Timing Analysis........................................................................................ - Running the TimeQuest Timing Analyzer - Tasks Pane......................................................................................... - Console.............................................................................................. - Report Pane - View Pane
- Classic Timing Analysis - Specifying Classic Timing Requirements - Specifying Project-Wide Classic Timing Settings........................ - Specifying Individual Timing Assignments - Performing a Classic Timing Analysis........................................................
- Performing an Early Timing Estimate....................................................................... - Classic Timing Analysis Reporting - Making Assignments & Viewing Delay Paths........................................... - Viewing Timing Delays with the Technology Map Viewer
- Performing Timing Analysis with EDA Tools.......................................................... - Using the PrimeTime Software - Using the Tau Software
- Chapter 10: Timing Closure.......................................................................................................
- Introduction...................................................................................................................
- Using the Chip Planner - Chip Planner Tasks And Layers................................................................... - Making Assignments.....................................................................................
- Achieve Timing Closure....................................................................................... Using Incremental Compilation to
- Using the Timing Optimization Advisor
- Using Netlist Optimizations to Achieve Timing Closure VI ■ INTRODUCTION TO THE QUARTUS II S OFTWARE A LTERA C ORPORATION
- Preserve Timing Using LogicLock Regions to
- Soft LogicLock Regions
- Path-Based Assignments...............................................................................
- Achieve Timing Closure Using the Design Space Explorer to
- Chapter 11: Power Analysis.......................................................................................................
- Introduction...................................................................................................................
- Power Analysis with the PowerPlay Power Analyzer............................................
- Specifying Power Analyzer Options
- Using the PowerPlay Early Power Estimator...........................................................
- Chapter 12: Programming & Configuration
- Introduction...................................................................................................................
- Programming One or More Devices With the Programmer
- Creating Secondary Programming Files - Creating Other Programming File Formats - Converting Programming Files....................................................................
- Using the Quartus II Software to Program Via a Remote JTAG Server................
- Chapter 13: Debugging
- Introduction...................................................................................................................
- Using the SignalTap II Logic Analyzer...................................................................... - Setting Up the SignalTap II Logic Analyzer - Using the SignalTap II Logic Analyzer with Incremental Compilation. - Analyzing SignalTap II Data.........................................................................
- Using an External Logic Analyzer
- Using SignalProbe
- Using the In-System Memory Content Editor..........................................................
- Using the In-System Sources and Probes Editor......................................................
- Using the RTL Viewer & Technology Map Viewer For Debugging
- Debugging Using the Chip Planner for
- Chapter 14: Engineering Change Management......................................................................
- Introduction...................................................................................................................
- Identifying Delays & Critical Paths With the Chip Planner...................................
- Editing Atoms in the Chip Planner............................................................................
- Modifying Resource Properties With the Resource Property Editor
- Viewing & Managing Changes with the Change Manager....................................
- Verifying ECO Changes
- Chapter 15: Formal Verification
- Introduction...................................................................................................................
- Using the Cadence Encounter Conformal Software................................................
- Specifying Additional Settings
- Chapter 16: System-Level Design............................................................................................. ALTERA CORPORATION INTRODUCTION TO THE QUARTUS II S OFTWARE ■ VII
- Introduction...................................................................................................................
- Creating SOPC Designs with SOPC Builder
- Creating the System.......................................................................................
- Generating the System
- Creating DSP Designs with the DSP Builder
- Instantiating Functions..................................................................................
- Generating Simulation Files
- Generating Files for Synthesis......................................................................
- Chapter 17: Installation, Licensing & Technical Support......................................................
- Installing the Quartus II Software..............................................................................
- Licensing the Quartus II Software
- Getting Technical Support...........................................................................................
- Chapter 18: Documentation & Other Resources
- Getting Online Help.....................................................................................................
- Starting the Quartus II Interactive Tutorial
- Other Quartus II Software Documentation
- Other Altera Literature
- Index
The Settings Dialog Box................................................................................................. IV ■ INTRODUCTION TO THE QUARTUS II S OFTWARE A LTERA C ORPORATION
Preface
The Altera ®^ Quartus ®^ II design software is the most comprehensive environment available for system-on-a-programmable-chip (SOPC) design. This manual is designed for the novice Quartus II software user and provides an overview of the capabilities of the Quartus II software in programmable logic design. It is not, however, intended to be an exhaustive reference manual for the Quartus II software. Instead, it is a guide that explains the features of the software and how these can assist you in FPGA and CPLD design. This manual is organized into a series of specific programmable logic design tasks. Whether you use the Quartus II graphical user interface, other EDA tools, or the Quartus II command-line interface, this manual guides you through the features that are best suited to your design flow.
The first chapter gives an overview of the major graphical user interface, EDA tool, and command-line interface design flows. Each subsequent chapter begins with an introduction to the specific purpose of the chapter, and leads you through an overview of each task flow. It shows you how to integrate the Quartus II software with your existing EDA tool and command-line design flows. In addition, the manual refers you to other resources that are available to help you use the Quartus II software, such as Quartus II online Help and the Quartus II interactive tutorial, application notes, white papers, and other documents and resources that are available on the Altera website.
Use this manual to learn how the Quartus II software can help you increase productivity and shorten design cycles; integrate with existing programmable logic design flows; and achieve design, performance, and timing requirements quickly and efficiently.
TABLE OF CONTENTS
Using Netlist Optimizations to Achieve Timing Closure VI ■ INTRODUCTION TO THE QUARTUS II S OFTWARE A LTERA C ORPORATION
Terminology
The following table shows terminology that is used throughout the Introduction to the Quartus II Software manual:
Term Meaning “click” Indicates a quick press and release of the left mouse button. It also indicates that you need to use a mouse or key combination to start an action. “double-click” Indicates two clicks in rapid succession. “select” Indicates that you need to highlight text and/or objects or an option in a dialog box with a key combination or the mouse. A selection does not start an action. For example: Select Chain Description File , and then click OK. “point” Indicates that you need to position the mouse pointer, without clicking, at an appropriate location on the screen, such as a menu or submenu. For example: On the Help menu, point to Altera on the Web , and then click Quartus II Service Request. turn on/turn off Indicates that you must click a check box to turn a function on or off.
Design Flow
What’s in Chapter 1:
Introduction 2
Graphical User Interface Design Flow 3
EDA Tool Design Flow 9
Design Methodologies & Design Planning 14
Chapter
One
C HAPTER 1: D ESIGN F LOW GRAPHICAL U SER INTERFACE D ESIGN F LOW
ALTERA CORPORATION INTRODUCTION TO THE QUARTUS II S OFTWARE ■ 3
Graphical User Interface Design
Flow
You can use the Quartus II software graphical user interface to perform all stages of the design flow. Figure 2 shows the Quartus II GUI as it appears when you first start the software.
Figure 2. Quartus II Graphical User Interface
The Quartus II software includes a modular Compiler. The Compiler includes the following modules (modules marked with an asterisk are optional during a full compilation, depending on your settings):
■ Analysis & Synthesis ■ Partition Merge* ■ Fitter
C HAPTER 1: DESIGN F LOW
Graphical User Interface Design Flow
4 ■ INTRODUCTION TO THE QUARTUS II S OFTWARE A LTERA C ORPORATION
■ Assembler* ■ TimeQuest Timing Analyzer or Classic Timing Analyzer* ■ Design Assistant* ■ EDA Netlist Writer* ■ HardCopy ®^ Netlist Writer*
To run all Compiler modules as part of a full compilation, on the Processing menu, click Start Compilation. You can also run each module individually by pointing to Start on the Processing menu, and then clicking the command for the module you want to start. You can also run some of the Compiler modules incrementally. See “Top-Down Incremental Compilation Flow” on page 15 for more information.
In addition, to start the Compiler modules individually, click Compiler Tool on the Processing menu and run each module from the Compiler Tool window (Figure 3). The Compiler Tool window also allows you to open the settings file or report file for the module, or to open other related windows.
Figure 3. Compiler Tool Window
The Quartus II software also provides predefined compilation flows that you can use with commands on the Processing menu. Table 1 lists the commands for some of the most common compilation flows.
Start module Open module settings page Open report file
C HAPTER 1: DESIGN F LOW GRAPHICAL U SER INTERFACE DESIGN FLOW
6 ■ INTRODUCTION TO THE QUARTUS II S OFTWARE A LTERA C ORPORATION
Figure 4. Customize Dialog Box
The Customize dialog box also allows you to choose whether you want the optional Quartus II or the MAX+PLUS II quick menus to display, and whether you want them on the right or left side of the menu bar. The Quartus II quick menu contains menu commands for each Quartus II application and common processing commands. The MAX+PLUS II quick menu provides commands for applications and common MAX+PLUS II menu commands. The commands on the MAX+PLUS II menu perform the same functions as the corresponding Quartus II commands. Figure 5 shows the Quartus II and MAX+PLUS II quick menus.
C HAPTER 1: D ESIGN F LOW GRAPHICAL U SER INTERFACE D ESIGN F LOW
ALTERA CORPORATION INTRODUCTION TO THE QUARTUS II S OFTWARE ■ 7
Figure 5. Quartus II and MAX+PLUS II Quick Menus
MAX+PLUS II Quick Menu
Quartus II Quick Menu
