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Programmable Logic Design

Quick Start Hand Book

By Karen Parnell & Nick Mehta

January 2002

Second

Edition

Programmable Logic Design Quick Start Hand Book Page 2

ABSTRACT

Whether you design with discrete logic, base all of your designs on microcontrollers, or simply want to learn how to use the latest and most advanced programmable logic software, you will find this book an interesting insight into a different way to design.

Programmable logic devices were invented in the late seventies and since then have proved to be very popular and are now one of the largest growing sectors in the semiconductor industry. Why are programmable logic devices so widely used? Programmable logic devices provide designers ultimate flexibility, time to market advantage, design integration, are easy to design with and can be reprogrammed time and time again even in the field to upgrade system functionality.

This book was written to complement the popular Xilinx Campus Seminar series but can also be used as a stand-alone tutorial and information source for the first of your many programmable logic designs. After you have finished your first design this book will prove useful as a reference guide or quick start handbook.

The book details the history of programmable logic, where and how to use them, how to install the free, full functioning design software (Xilinx WebPACK ISE included with this book) and then guides you through your first of many designs. There are also sections on VHDL and schematic capture design entry and finally a data bank of useful applications examples.

We hope you find the book practical, informative and above all easy to use.

Karen Parnell & Nick Mehta

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NAVIGATING THE BOOK

This report was written for both the professional engineer who has never designed using programmable logic devices and for the new engineer embarking on their exciting career in electronics design. To accommodate this the following navigation section has been written to help the reader decide in advance which section he/she wishes to read.

This chapter gives an overview of how and where programmable logic devices are used. It gives a brief history of the programmable logic devices and goes on to describe the different ways of designing with PLDs.

Chapter 2 describes the products and services offered by Xilinx to ensure PLD designs enable time to market advantage, design flexibility and system future proofing. The Xilinx portfolio includes both CPLD & FPGA devices, design software, design services & support, and Cores.

The WebPACK ISE design software offers a complete design suite based on the Xilinx Foundation ISE series software. This chapter describes how to install the software and what each module does.

Chapter 2 Xilinx Solutions

Chapter 3 WebPACK ISE Design Software

Chapter 1 Introduction

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NAVIGATING THE BOOK (Continued)

This section is a step by step approach to your first simple design. The following pages are intended to demonstrate the basic PLD design entry implementation process.

This chapter discusses the Synthesis and implementation process for FPGAs. The design targets a Spartan IIE FPGA.

This section takes the VHDL or Schematic design through to a working physical device. The design is the same design as in the previous chapters but targeting a CoolRunner CPLD.

The final chapter contains a useful list of design examples and applications that will give you a good jump-start into your future programmable logic designs. It will also give you pointers on where to look for and download code and search for Intellectual Property (IP) Cores from the Xilinx Web site.

Chapter 4 WebPACK ISE Design Entry

Chapter 5 Implementing FPGAs

Chapter 7 Design Reference Bank

Chapter 6 Implementing CPLDs

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CONTENTS (Continued)

2.5.1 ESP Emerging

Standards and Protocols

2.5.2 Xtreme DSP

2.5.3 Xilinx at Work

2.5.4 Xilinx On Line

2.5.5 Configuration Solutions

2.5.6 Processor Central

2.5.7 Memory Corner

2.5.8 Wireless Connection

2.5.9 Networking Connection

2.5.10 Video and Image

Processing

2.5.11 Computers

2.5.12 Communications and

Networking

2.5.13 Education Services

2.5.14 University Program

2.5.15 Design Consultants

2.5.16 Technical Support

Chapter 3 WebPACK ISE DESIGN

SOFTWARE

3.1 Module Descriptions

3.2 WebPACK CDROM Installation

Instructions

3.3 Getting Started

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CONTENTS (Continued)

Chapter 4 WebPACK ISE DESIGN ENTRY

4.1 Creating a project

4.2 VHDL Design Entry

4.3 Functional Simulation

4.4 State Machine Editor

4.5 Top Level VHDL Designs

4.6 Top Level Schematic Designs

Chapter 5 IMPLEMENTING FPGAS

5.1 Synthesis

5.2 Constraints Editor

5.3 Reports

5.4 Timing Simulation

5.5 Configuration

Chapter 6 IMPLEMENTING CPLDS

6.1 Synthesis

6.2 Constraints Editor

6.3 Reports

6.4 Timing Simulation

6.5 Programming

Chapter 7 DESIGN REFERENCE BANK

7.1 Introduction

7.2 Get the Most out of Microcontroller-

Based Designs: Put a Xilinx CPLD

Onboard

7.3 Application Notes and Example Code

7.4 Website Reference

GLOSSARY OF TERMS

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ABBREVIATIONS (Continued)

MPEG Motion Picture Experts Group

MSB Most Significant Bit

NRE Non-Recurring Engineering (Cost)

PAL Programmable Array Logic device

PCB Printed Circuit Board

PCI Peripheral Component Interconnect

PCMCIA Personal Computer Memory Card

International Association

PCS Personnel Communications System

PLA Programmable Logic Array

PLD Programmable Logic Device

PROM Programmable Read Only Memory

EPROM Erasable Programmable Read Only Memory

RAM Random Access Memory

ROM Read Only Memory

SPLD Simple Programmable Logic Device

SRAM Static Random Access Memory

SRL16 Shift Register LUT

Tpd Time of Propagation Delay through the device

UMTS Universal Mobile Telecommunications System

VHDL VHISC High Level Description Language

VHSIC Very High Speed Integrated Circuit

VSS Visual Software Solutions

WLAN Wireless Local Access Network

XST Xilinx Synthesis Technology

QML Qualified Manufacturers Listing

QPRO  QML Performance Reliability of supply Off-

the-shelf ASIC

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INTRODUCTION

The following chapter gives an overview of how and where programmable logic devices are used. It gives a brief history of the programmable logic devices and goes on to describe the different ways of designing with PLDs.

1.1 The History of Programmable Logic

By the late 70’s, standard logic devices were the rage and printed circuit boards were loaded with them. Then someone asked the question: “What if we gave the designer the ability to implement different interconnections in a bigger device?” This would allow the designer to integrate many standard logic devices into one part. In order to give the ultimate in design flexibility Ron Cline from Signetics (which was later purchased by Philips and then eventually Xilinx!) came up with the idea of two programmable planes. The two programmable planes provided any combination of ‘AND’ and ‘OR’ gates and sharing of AND terms across multiple OR’s.

This architecture was very flexible, but at the time due to wafer geometry's of 10um the input to output delay or propagation delay (Tpd) was high which made the devices relatively slow.

Introduction Chapter 1

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Figure 1.2 SPLD Architectures

The architecture has a mesh of horizontal and vertical interconnect tracks. At each junction, there is a fuse. With the aid of software tools, the user can select which junctions will not be connected by “blowing” all unwanted fuses. (This is done by a device programmer or more commonly nowadays using In-System Programming or ISP). Input pins are connected to the vertical interconnect and the horizontal tracks are connected to AND-OR gates, also called “product terms”. These in turn connect to dedicated flip-flops whose outputs are connected to output pins.

PLDs provided as much as 50 times more gates in a single package than discrete logic devices! A huge improvement, not to mention fewer devices needed in inventory and higher reliability over standard logic.

Programmable Logic Device (PLD) technology has moved on from the early days with such companies as Xilinx producing ultra low power CMOS devices based on Flash technology. Flash PLDs provide the

Introduction Chapter 1

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ability to program the devices time and time again electrically programming and ERASING the device! Gone are the days of erasing taking in excess of twenty minutes under an UV eraser.

1.2 Complex Programmable Logic Devices (CPLDs)

Complex Programmable Logic Devices (CPLD) are another way to extend the density of the simple PLDs. The concept is to have a few PLD blocks or macrocells on a single device with general purpose interconnect in between. Simple logic paths can be implemented within a single block. More sophisticated logic will require multiple blocks and use the general purpose interconnect in between to make these connections.

Figure 1.3 CPLD Architecture

CPLDs are great at handling wide and complex gating at blistering speeds e.g. 5ns which is equivalent to 200MHz. The timing model for CPLDs is easy to calculate so before you even start your design you can calculate your in to output speeds.

Introduction Chapter 1

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Reduced Board Area: CPLDs offer a high level of integration (large number of system gates per area) and are available in very small form factor packages. This provides the perfect solution for designers of products which must fit into small enclosures or who have a limited amount of circuit board space to implement the logic design. The CoolRunner CPLDs are available in the latest chip scale packages, e.g. CP56 which has a pin pitch of 0.5mm and is a mere 6mm by 6mm in size so are ideal for small, low power end products.

Cost of Ownership: Cost of Ownership can be defined as the amount it costs to maintain, fix, or warranty a product. For instance, if a design change requiring hardware rework must be made to a few prototypes, the cost might be relatively small. However, as the number of units that must be changed increases, the cost can become enormous. Because CPLDs are re-programmable, requiring no hardware rework, it costs much less to make changes to designs implemented using them. Therefore cost of ownership is dramatically reduced. And don't forget the ease or difficulty of design changes can also affect opportunity costs. Engineers who are spending a lot of time fixing old designs could be working on introducing new products and features - ahead of the competition.

There are also costs associated with inventory and reliability. PLDs can reduce inventory costs by replacing standard discrete logic devices. Standard logic has a predefined function and in a typical design lots of different types have to be purchased and stocked. If the design is changed then there may be excess stock of superfluous devices. This issue can be alleviated by using PLDs i.e. you only need to stock one device and if your design changes you simply reprogram. By utilising one device instead of many your board reliability will increase by only picking and placing one device instead of many. Reliability can also be increased by using the ultra low power CoolRunner CPLDs i.e. lower heat dissipation and lower power operation leads to decreased Failures In Time (FIT).

Introduction Chapter 1

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1.3 Field Programmable Gate Arrays (FPGAs)

In 1985, a company called Xilinx introduced a completely new idea. The concept was to combine the user control and time to market of PLDs with the densities and cost benefits of gate arrays. A lot of customers liked it - and the FPGA was born. Today Xilinx is still the number one FPGA vendor in the world!

An FPGA is a regular structure of logic cells or modules and interconnect which is under the designer’s complete control. This means the user can design, program and make changes to his circuit whenever he wants. And with FPGAs now exceeding the 10 million gate limit (Xilinx Virtex II is the current record holder), the designer can dream big!

Figure 1.4 FPGA Architecture

With the introduction of the Spartan range of FPGAs we can now compete with Gate Arrays on all aspects - price, gate and I/O count,

Introduction Chapter 1

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In the SRAM logic cell, instead of conventional gates there is instead a Look Up Table (LUT) which determines the output based on the values of the inputs. (In the “SRAM logic cell” diagram above you can see 6 different combinations of the 4 inputs that will determine the values of the output). SRAM bits are also used to make connections.

One-time programmable (OTP) FPGAs use anti-fuses (contrary to fuses, connections are made not “blown” during programming) to make permanent connections in the chip and so do not require a SPROM or other means to download the program to the FPGA. However, every time you make a design change, you must throw away the chip! The OTP logic cell is very similar to PLDs with dedicated gates and flip- flops.

Design Integration

The integration of 74 series standard logic into a low cost CPLD is a very attractive proposition. Not only do you save Printed Circuit Board (PCB) area and board layers therefore reducing your total system cost but you only have to purchase and stock one generic part instead of upto as many as twenty pre-defined logic devices. In production the pick and place machine only has to place one part - therefore speeding up production. Less parts means higher quality and better Failure In Time (FIT) factor.

By using Xilinx CoolRunner devices (our family of ultra low power parts) in a design customers can benefit from low power consumption and reduced thermal emissions. This in turn leads to the reduction of the use of heat sinks (another cost saving) and a higher reliability end product.

Introduction Chapter 1

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Figure 1.6 Basic Logic Definitions

1.4 The Basic Design Process

The availability of design software such as WebPACK ISE has made it much easier to design with programmable logic. Designs can be described easily and quickly using either a description language such as ABEL (Advanced Boolean Expression Language), VHDL (VHSIC Hardware Description Language), Verilog or via a schematic capture package.

Schematic capture is the traditional method that designers have used to specify gate arrays and programmable logic devices. It is a graphical tool that allows the designer to specify the exact gates he requires and how he wants them connected. There are 4 basic steps to using schematic capture.