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Material Type: Exam; Class: Digit Integrat Circ; Subject: Electrical Engineering And Computer Science; University: University of Michigan - Ann Arbor; Term: Fall 2007;
Typology: Exams
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Fall 2007
Midterm 1 Solution
Problem 1 Note that capacitances and delays have nothing to do with VTC!
a) No effect. b) VTC shifts right. c) VTC shifts left. d) Can never be the same since tpLH = 0.69RpC, tpHL = 0.69(Rp||Rn)C, Rp would have to equal RpRn/(Rp+Rn).
Problem 2 a)
b)
c) No, only sub-threshold leakage.
I1 has no short circuit current since we assume the rise and fall times are zero. I2 has the following short circuit current:
t (^) sc,fall = VDD – 2VT tf VDD 0. = (2.5 – 0.8)/2.5 * (82.7e-12 / 0.8) = 70 ps
t (^) sc2,rise = VDD – 2VT tr VDD 0. = (2.5 – 0.8)/2.5 * (100e-12 / 0.8) = 85 ps
*Psc = 155e-12 * 2.5 * 100e-6 * 1.25e = 0.48 mW
tf = 2.2 Reqn C 1 = 1.21 * C 1 * VDD / I (^) DSAT,N = 1.21 * 10e-15 * (2.5 / (731 * 0.5 μA) ) = 82.7 ps
tr = 2.2 Reqp C 1 = 1.21 * C 1 * VDD / I (^) DSAT,P = 1.21 * 10e-15 * (2.5 / (300 * 1.0 μA) ) = 100 ps
b) (5 pts) What happens to my total power dissipation if I reduce Wp , Wn and t (^) ox of both inverters by a factor S (where S > 1) while keeping the same VDD and V (^) T? Be concise and clear in your answer; use equations when necessary.
For dynamic, if C’s don’t scale: Pdyn = (C 1 VDD^2 + C 2 VDD^2 ) f (no scaling)
If C’s scale: Pdyn = ((C 1 / S )VDD2 + (C 2 / S )VDD^2 ) f Pdyn/S
Pstat = 2 (I (^) static,n / S + I (^) static,p / S ) VDD = Pstat / S
Psc = t (^) sc,rise VDD I (^) peak f + t (^) sc,fall VDD I (^) peak f ∝ tf * Ipeak + tr * Ipeak ∝ (S*tf) (Ipeak/S) + (Str) *(Ipeak/S) ∝ 1 (no scaling)
The only trick here was to remember that Ipeak ∝ I (^) SAT ∝ W. This scaling situation might be the case when wiring capacitances dominate the gate caps (such that scaling Cg’s doesn’t really affect the power scaling).
