ECE 2030 D Computer Engineering Spring 2012
4 problems, 5 pages Exam Three Solutions 12 April 2012
Problem 1 (3 parts, 30 points) Memory Systems
Part A (12 points) Consider a 1 Gbit DRAM chip organized as 32 million addresses of 32-bit words.
Assume both the DRAM cell and the DRAM chip are square. The column number and offset concatenate
to form the memory address. Using the organization approach discussed in class, answer the following
questions about the chip. Express all answers in decimal (not powers of two).
total number of bits in address log(32M) = log(225) = 25
number of columns
√
230=215=32K
column decoder required (n to m)15 to 32K
number of words per column 215/25 = 210 = 1K
type of mux required (n to m)1K to 1
number of address lines in column offset 10
Part B (10 points) Consider an 8 Gbyte memory system with 1 billion addresses of 64-bit words using
a 32 million address by 32-bit word memory DRAM chip.
word address lines for memory system log(1B) = log(230) = 30
chips needed in one bank 2
banks for memory system 230/225 = 25 = 32
memory decoder required (n to m)5 to 32
DRAM chips required 64
Part C (8 points) Design a 8 million address by 4 bit memory system with 4M x 4 memory chips. Label
all busses and indicate bit width. Assume R/W is connected and not shown here. Use a bank decoder if
necessary. Be sure to include the address bus, data bus, and MSEL.
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