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UIUC ECE512: Computer Microarchitecture: Hardware and Software
© 2005, Wen-mei W. Hwu, All Rights Reserved.
1
Compile-Time Data
Speculation
Wen-mei Hwu
Dept. of ECE
University of Illinois
at Urbana-Champaign
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Computer Microarchitecture: Data Speculation and Memory Conflict Buffer, Study notes of Computer Architecture and Organization
An excerpt from the university of illinois at urbana-champaign (uiuc) ece512 course notes on computer microarchitecture. It discusses data speculation, its types, and the memory conflict buffer (mcb) technique to deal with dependence conditions and exploit parallelism. The document also covers motivations, applications, and key issues related to runtime memory disambiguation.
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Compile-Time Data
Speculation
Wen-mei Hwu Dept. of ECE University of Illinois at Urbana-Champaign
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Types of Data Speculation
- Compile-time Data Speculation
- executing an instruction before knowing input is up to date - Dependence Speculation - moving a load and its use above a potentially conflicting store - must correct the load and the uses thus moved in case of conflict
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Load/Store Dependence
Conditions
STORE (addr1) <- R LOAD R2 <- (addr2)
- Always access the same location
- redundant load elimination
- Never access the same location
- load/store reordering
- Never access the same location
- redundant load elimination
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Load/Store Dependence
Conditions
- May access the same location
- They sometimes access the same location - No conclusion can be reached • How often do they access the same location?
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Memory Conflict Buffer
- Deals with very frequent or very infrequent dependence conditions - Allows uses of the load value to move above the store - Eliminates effect of memory dependence to exploit parallelism
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Data Spec. Motivations
- Lower entrance level requirement of static disambiguation - Achieve performance earlier and more consistently for - new languages, e.g., C -> C++ • new applications and libraries - e.g., object oriented and dynamically linked - Allow performance to increase smoothly as static disambiguationmatures
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Runtime Memory
Disambiguation
- See figure
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Key Issues
- Number of explicit comparisons • Amount of conflict correction code • Varying access sizes • Potential payoff in performance vs. overhead and resourceconsumption
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Preload Register Update
- Register State Bits (See figure)
- P: preload register, coherence mechanism on - F: freeze state for I/O ports • R: ready bit for interlocking mechanism - T: trap bit for exception detection • Preload Type: size and data alignment
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Example Pipeline Timing
and Code Example
- See figures
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PRU Subset Operation
- Save preload address in an empty address register - Set V bit and GRP entry • Use of preload destination register will turn off coherence
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Address Register
Replacement
- An old entry is overwritten • Set F bit of GR associated with the replaced entry - Replaced register is reloaded with address field at time of use
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Compiler Terms
–The first ambiguous store before the memory operation
- Closest ambiguous store after
(CASA):
–The first ambiguous store after the memory operation
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Dependence Graph
- Remove all previous store dependence to potential preloads - Insert dependence arc from CASB to USE