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The Computer System and its Interconnection Structures, Lecture notes of Computer Architecture and Organization

Petronas Technology UniversityComputer Architecture and Organization

Chapter 3 , Computer Architecture ; Computer Organization: The Computer System and its Interconnection Structures

Typology: Lecture notes

2011/2012

Uploaded on 08/11/2012

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EE 4504 Section 2 1
EE 4504
Computer Organization
Section 2
The Computer System and its
Interconnection Structures
EE 4504 Section 2 2
System Components
At the global and processor levels of
computer design, we are concerned about
four component “primitives”
–CPUs
»ALUs
»Control units
–Memories
–I/O devices
–Interconnection structures
Knowledge of these components and their
operation (interaction) offers insight into
system bottlenecks, alternate pathways,
magnitude of system failures, and
opportunities for performance
enhancement
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EE 4504 Section 2 1

EE 4504

Computer Organization

Section 2

The Computer System and its

Interconnection Structures

EE 4504 Section 2 2

System Components

At the global and processor levels of

computer design, we are concerned about

four component “primitives”

  • CPUs » ALUs » Control units
  • Memories
  • I/O devices
  • Interconnection structures

Knowledge of these components and their

operation (interaction) offers insight into

system bottlenecks, alternate pathways,

magnitude of system failures, and

opportunities for performance

enhancement

EE 4504 Section 2 3

von Neumann’s Architecture

von Neumann is credited with developing

the idea of controlling the operation of

hardware through the manipulation of

control signals

  • First machines (e.g., ENIAC) had to be physically rewired to change the computation being performed
  • von Neumann used the memory of the computer to store the sequence of the control signal manipulations required to perform a task -- software programming
  • the von Neumann architecture has been the basis for virtually all computer designs since the first generation

EE 4504 Section 2 4

Characteristics

  • Both data and instructions (control sequences) are stored in a single read-write memory » Can not tell the difference between data and instructions by examining a memory location
  • Memory contents are addressable by location without regard for the type of data contained there
  • Execution occurs in a sequential fashion by reading consecutive instructions from memory

Instruction codes

Instruction Interpreter (control unit)

Arithmetic logic unit

Data in (^) Results out

EE 4504 Section 2 7

Figure 3.8 Transfer of control via interrupts

EE 4504 Section 2 8

Interrupts are processed in an interrupt

cycle within the overall instruction cycle

  • At the end of an instruction cycle (operand storage step), check to see if any interrupts are pending
  • If there aren’t any, proceed with the next instruction
  • If there are » Suspend execution of the program and save its “state” » Jump to the interrupt service routine and resume the “normal” instruction cycle » When the ISR is completed, restore the state of the program and resume its operation

EE 4504 Section 2 9

Multiple interrupts

  • A typical system can support several to several dozen interrupts
  • How should the system respond if more than 1 interrupt occurs at the same time? » Systems prioritize the various interrupts » At the start of the interrupt cycle, the highest priority pending interrupt will be serviced » Remaining interrupt requests will be serviced in turn
  • What if an interrupt occurs while an ISR is being executed (a result of a previous interrupt) » Ignore the second interrupt (by disabling interrupts) until the ISR completes -- e.g., MC68HC11 microcontroller » Recognize and service the interrupt only if it has a higher priority than the one currently being serviced -- e.g., 8085

EE 4504 Section 2 10

Figure 3.13 Transfer of control with multiple interrupts

EE 4504 Section 2 13

Bus performance limited by

  • Data propagation delay through the bus -- longer buses (to support more devices) require longer delays
  • Aggregate demand for access to the bus from all devices connected to the bus

To avoid bottlenecks, multiple buses are

used in most systems

  • Hierarchical
  • High-speed limited access buses close to the processor
  • Slower-speed general access buses farther away from the processor

EE 4504 Section 2 14

Figure 3.18 Hierarchical bus configurations

EE 4504 Section 2 15

Bus arbitration

  • Process of insuring only 1 devices places information onto the bus at a time
  • Master - slave mechanism » Master is given control of the bus and can place information onto it » Slave receives the information from the master
  • Two methods » Centralized Central bus controller mediates all device requests for the bus » Decentralized No centralized controller All devices contain logic to control access to the bus

EE 4504 Section 2 16

Bus timing

  • Synchronous » Occurrence of events on the bus is determined by the clock » All events start at the beginning of a clock cycle » Example: PCI bus
  • Asynchronous » The occurrence of one event follows and depends onthe occurrence of a previous event » More flexible than synchronous bus but more complicated as well » Accomodates wider range of device speeds » Example: Futurebus+

EE 4504 Section 2 19

  • 8-bit bus » First used in the PC-XT » 62 pins » 4.77 MHz clock » 20 address lines -- 1 Mword memory » 8 data lines » 6 interrupt lines, 2 DMA channels
  • 16-bit bus » 8-bit bus was very limiting » 16-bit bus introduced with the PC-AT and the 80286 » Augmented the existing 8-bit bus’ 62-pin connector with a 36-pin connector » 8.33 MHz clock » Total of 24 address lines -- 16 MB address space » 16 data lines » 5 more interrupt lines and 4 more DMA channels

EE 4504 Section 2 20

Micro Channel Architecture

  • Introduction of ‘386 and then ‘486 processors put a strain on the performance of the ISA bus » Slow to pass 32-bit data words in 2 bus operations
  • IBM wanted to put ISA to rest and introduced the MCA in their PS/2 series of machines (late 80s)
  • Offered many improvements over the ISA » Higher speed » Bus arbitration » Automatic configuration
  • 16 and 32-bit implementations
  • Proprietary architecture that never caught on with users » Limited peripheral support » Large installed base of ISA equipment and low-cost replacements

EE 4504 Section 2 21

EISA (Extended-ISA)

  • Introduced in ‘88-89 to provide enhancements to the ISA bus
  • 16/32-bit data
  • 24/32-bit address
  • 8.33 MHz
  • Backward compatible with ISA equipment
  • Roughly twice the data throughput of ISA
  • More interrupts and DMA channels
  • Never really caught on -- viewed as a bus for “high-end” machines

EE 4504 Section 2 22

VESA Video Local Bus

  • Video Electronics Standards Assoc.
  • Give video and graphics peripherals quick access to main memory
  • Implemented in conjunction with ISA or EISA for support of other peripherals (2 sets of connectors on motherboard)
  • 32/64-bit data, 24/32-bit address
  • Speed related to speed of the processor

CPU

Bus drivers and glue logic

Memory

Keyboard

ISA Bus

Bus slots

VL Bus slots

EE 4504 Section 2 25

Futurebus+

  • High-performance asynchronous bus
  • Introduced in the late 80s
  • Architecture, processor, and technology independent
  • Support: » Parallel and arbitration protocols » Fault tolerant and high-reliability systems » Cache-based memory
  • Has the potential to supplant other buses because of its flexibility » Can support data bus widths of up to 256 bits
  • Flexibility comes at a higher implementation cost than the PCI bus -- so would appeal to a different target user

EE 4504 Section 2 26

Summary

System architecture

  • von Neumann structure
  • Instruction execution cycle

Interrupts

  • Brief overview!
  • Purpose and implementation
  • Multiple interrupts

Bus interconnections

  • Need for them
  • Survey of common buses
  • See Bigelow, Stephen,“Understanding PC Buses,” Circuit Cellar Ink, The Computer Applications Journal , No. 50, September 1994, pp. 44-