Download Verilog Homework 1: Completing Digital Circuits for Comparison - Prof. A. Skavantzos and more Assignments Electrical and Electronics Engineering in PDF only on Docsity!
EE 3755 Homework 1 Due: Oct 24, 2007
Estimated time to solve:
Prob. 1 30 minutes.
Prob. 2 30 minutes.
Prob. 3 30 minutes.
Prob. 4 30 minutes.
Preparing text files 1 hour.
Total 3 hours.
How to submit?
// No hard copy.
// Name your program file as hw1.v
// Name your script file as hw1.txt
// Leave your program file(hw1.v) and
// your script file(hw1.txt) on the class account.
Finish your program file(hw1,v) first, then do the followings:
Use “script hw1.txt “ command // To take a snap shot of your program. If you don’t know
// script command, look at the handout.
Use “cat hw1.v” command // To display contents of your program.
Use “ncverilog hw1.v” // To run your program.
then stop the script.
Example) SUN>script hw1.txt
SUN>cat hw1.v
SUN>ncverilog hw1.v
SUN> ( stop script by pressing CTRL-D)
AB_eq_i_1 AB_eq_i
Ai Bi
Fig.1 One_Bit_AND Slice. (one_AND gate,one_OR gate , three inputs and one output) //Circuit for the Problem 1.
A 0
AB_eq_
One_Bit_AND_Slice
One-bit-slice AB_eq_
B 0 A 1 B 1
One_Bit_AND_Slice
AB_eq_ Fig.2 Two One_Bit_And Slices( cascaded for the problem 3.)
Complete the module three_bit_comparator by using three one-bit-comparators.
For example) if three-bit inputs a=111, b= 111 then AeqB is 1 and AgtB is 0. if three-bit inputs a=110, b= 10 0 then AeqB is 0 and AgtB is 1. /// LSU EE 3755 Fall 2007 Verilog_Homework 1- Program template. /// Instructions: // // Copy this to a file( name it hw1.v) and save on your class account. // Use this file for your solution. //Your entire solution should be on this file. // Do not rename the modules in this file and be sure to use the filename given above. //////////////////////////////////////////////////////////////////////////////// /// Problem 0 module hello(); initial begin //display your name and class account. // Write your code here. // for example // if your name is "Clark Kent" and class account is ee // the exact answer will be: $display("ee375501 Clark Kent\n"); //simply change the account number and name. end endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 1 module one_bit_and_slice_ex(ab_eq_1,ab_eq_0,a,b); input a, b,ab_eq_0; output ab_eq_1; wire and_ab; // your solution goes here endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 2 module one_bit_and_slice_im(ab_eq_1,ab_eq_0,a,b);
input a, b,ab_eq_0; output ab_eq_1; // your solution goes here endmodule //////////////////////////////////////////////////////////////////////////////// /// Problem 3 module two_one_bit_and_slices (ab_eq_2,a,b,ab_eq_0); input [1:0] a, b; input ab_eq_0; output ab_eq_2; wire ab_eq_1; // your solution goes here // less than 3 lines. endmodule //////////////////////////////////////////////////////////////////////////////// //////////////////////////////////////////////////////////////////////////////// //// Problem 4 module one_bit_comparator(AeqB, AgtB, a, b, AeqBin, AgtBin); input a, b,AeqBin,AgtBin; output AeqB,AgtB; reg AeqB,AgtB; always begin if(a == b & AeqBin ==1) AeqB = 1; else AeqB = 0; if(a > b | (a ==b & AgtBin ==1)) AgtB = 1; else AgtB =0; #1; end endmodule //complete this module module three_bit_comparator(AeqB, AgtB, a, b); input [2:0] a, b; output AeqB,AgtB;
