CPSC 321:501-503 - Computer Architecture
Texas A&M University
Department of Computer Science
Fall 2006
Lab 5 - Introduction to Verilog (100 pts)
Complete by yourself
Release date: 16 October 2006
Due date: One week after the lab
Objective
In this lab, you will be introduced to Verilog. You will work on structural designs and specifications.
A simple example
Implementing a simple arbitrary Boolean function
Using primitive Verilog gates, implement the Boolean function: ab + a'. Name this module
first_module. Write a test bench - test_first - to examine the outputs for varying input
combinations. Compile the code with VCS and run the executable.
Here is what your Verilog code would look like:
module first_module(out, a, b);
input a, b;
output out;
wire a1, a2;
not n1(a1, a);
and and1(a2, a, b);
or or1(out,a1,a2);
endmodule
module test_first();
reg a, b;
wire out;
first_module fm(out,a,b);
initial begin
$monitor ($time,"\ta=%b\tb=%b\tout=%b",a,b,out);
a = 0; b = 0;
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CPSC 321
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Lab 5
9/1/2006
file://H:\web_courses\cpsc321\labs\lab5_06c.html
