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Computing Systems Organization

CT101 – Computing Systems

Contents

• Describe the operation of a computer at the functional level

• Explain the function of the main components of a computer

system

• Detail the interaction of computer sub-systems

• Detail the organization of computer sub-systems

Basic Computing Systems

Organization

System buses

• A bus is a set of wires, that interconnects all the

components (subsystems) of a computer

• Source component sources out data onto the bus, the

destination component inputs data from the bus

• A system may have a hierarchy of buses; it may use

its address, data and control buses to access memory

and an I/O controller. The I/O controller may use a

second bus, often described as I/O bus or local bus

to access a variety of attached devices

• PCI bus is an example of a very common local bus

Data bus

• When the CPU fetches data from memory, it first

outputs the address on the address bus, then the

memory outputs the data onto the data bus; the CPU

reads the data from data bus

• When writing data onto the memory, the CPU

outputs first the address on the address bus, then

outputs the data onto the output bus; memory then

reads and stores the data at the proper location

• The process to read/write to a I/O device is similar

Control bus

• Address and data buses consist of n lines, which

combine to transmit one n bit value; control bus is a

collection of individual control signals

• These signals indicate whether the data is to be read

into or written out the CPU, whether the CPU is

accessing memory or an IO device, and whether the

I/O device or memory is ready for the data transfer

• This bus is mostly a collection of unidirectional

signals

Programs: Instructions and Operands

• A program consists of a number of CPU instructions.
• Each instruction consists of:
  • an instruction code
  • one or more operand's (data which the instruction manipulates)
• The instruction specifies to the CPU what to do, where the data is located, and where the output data (if any) will be put.
• Instructions are held in the memory section of the computer system. Instructions are transferred one at a time into the CPU, where they are decoded then executed. Instructions follow each other in successive memory locations.
• Memory locations are numbered sequentially. The processor unit keeps track of the instruction it is executing by using a internal counter.
• This counter holds the location in memory of the instruction it is executing. Its name is the program counter (sometimes called instruction pointer ).

Von Neumann and Harvard architectures

• Von Neumann
  • Allows instructions and data to be mixed and stored in the same

memory module

• More flexible and easier to implement
• Suitable for most of the general purpose processors
• Harvard:
• Uses separate memory modules for instructions and for data
• It is easier to pipeline and there are no memory alignment

problems

• Higher memory throughput
• Suitable for DSP (Digital Signal Processors)

Computer Memory

• The processor selects a specific address in memory by placing the address on the address bus. The value on this address bus is used by the memory system to find the specific location within the chip which the processor is requiring access to.
• The total number of address locations which can be accessed by the processor is known as its physical address space. How large this is determined by the size of the address bus, and is often expressed in terms of Kilobytes (x1024) or Megabytes. - 16 bits address bus = 64K (65536 locations) - 20 bits address bus = 1MB (IBM PC) - 32 bits address bus = 4GB (486DX)
• Access Times Access time refers to how long it takes the processor to read or write to a specific memory location within a chip. The limiting factor is the type of technology used to implement the memory cells inside the chip.
• Volatility This refers to whether or not the contents of the memory is lost when power is turned off. If the contents are lost, the memory is volatile. If the contents are retained, then the memory is non-volatile.

Memory read/write operations

• a) Memory read operation

• b) Memory write operation

Cache

• Every address reference goes first to the cache; if the desired address is not here,

then we have a cache miss ;

• The contents are fetched from main memory into the indicated CPU register and the

content is also saved into the cache memory

• Most software exhibits temporal locality of access, meaning that it is likely that

same address will be used again soon, and if so, the address will be found in the cache, when we have a cache hit

• Transfers between main memory and cache occur at granularity of cache lines ,

around 32 or 64 bytes (rather than bytes or processor words). Burst transfers of this kind receive hardware support and exploit spatial locality of access to the cache (future access are often to address near to the previous one)

• Up to the type of write, caches can be
  • Write-through (when the update must be generated to the main memory as well as to the cache)
  • Write-back (when the update is generated only to the cache, that will propagate it to the main memory at a latter time)

Input/Output devices

• Peripheral devices allow input and output to occur.

• Examples of peripheral devices are

– disk drive controllers

– keyboards

– mice

– video cards

– parallel and serial cards

– real-time clocks

• The processor is involved in the initialization and

servicing of these peripheral devices.

CPU Function – Instruction cycle

• The instruction cycle is the procedure of processing an

instruction by the microprocessor:

• Fetches or reads the instruction from the memory
• Decodes the instruction, determining which instruction is to be

executed (which instruction has been fetched)

• Executes the instruction – performs the operations necessary to

complete what the instruction is suppose to do (different from

instruction to instruction, may read data from memory, may write

data to memory or I/O device, perform only operations within CPU

or combination of those)

• Each of the functions fetch -> decode -> execute consist of a

sequence of one or more operations inside the CPU (and

interaction with the subsystems)

Fetch Cycle

• In the first phase, the processor generates the necessary timing signals to fetch the next instruction from the memory system.
• The instruction is transferred from memory to an internal location inside the processor (the instruction register)
• In the above image, the processor is ready to begin the Fetch cycle. The current contents of the instruction counter (program counter) is address 0100. This value is placed on the address bus, and a READ signal is activated on the control bus. The memory receives this and finds the contents of the memory location 0100, which happens to be the instruction MOV AX, 0.
• The memory places the instruction on the Data Bus, and the processor then copies the instruction from the Data Bus to the Instruction Register.