April 20, 1998 page 1 S. Derenzo
Solutions for Midterm #2 - EECS 145M Spring 1998
PROBLEM 1
[The problem asked for a description in terms of specific characteristics- for example, just stating
that the flash converter is “fast” without a description caused a one point deduction]
1a Successive Approximation
•The conversion accuracy is limited by the resistor accuracy in the internal D/A- can easily be
16 bits. [1 point off for “no limit”] [OK for “large number”]
•The differential linearity is limited by the resistor accuracy in the internal D/A
•Relatively low cost, one D/A, one comparator, digital control circuits
•Speed is good, takes N cycles to determine N bits [2 points off for 2N steps to convert]
•An external sample and hold amplifier is needed to assure a constant input during conversion
1b Flash
•Number of bits is limited by the number of resistors and comparators that can be integrated
onto a single chip- 8-12 bits was OK for full credit.
•The differential linearity is limited by the resistor accuracy
•High cost- 2N resistors and 2N–1 comparators needed
•Speed is very good- conversion is continuous
•no external circuits are needed
1c Integrating or dual slope
•Number of bits is limited by the clock speed and the maximum acceptable conversion time.
•The differential linearity is excellent- limited by the clock accuracy and integrator linearity
•Medium cost- not many components but the integrator must be very linear
•Speed is very poor- requires 2N cycles to convert a full-scale input
•no external circuits are needed
1d Half flash
•Number of bits is limited to 10-12 (no reason it could not be as high as 16).
•The differential linearity is limited by the accuracy of the resistors and the linearity of the
difference amplifier
•Medium cost- requires only two N/2-bit flash converters and an accurate difference amplifier
•Speed is very good- conversion takes only two steps
•for best accuracy, a sample and hold amplifier is needed to keep the input constant during the
two steps
PROBLEM 2
2a v = 10 m/s f = 100 kHz (1 + 10/2000) = 100,500 Hz
v = 11 m/s f = 100 kHz (1 + 11/2000) = 100,550 Hz
v = 200 m/s f = 100 kHz (1 + 200/2000) = 110,000 Hz
[the more accurate f = 100 kHz/(1-200/2000) = 111,111 Hz, either was OK]
2b ∆f = 50 kHz, so length of sampling window S = 1/∆f = 0.02 s
2c The spectral leakage from 100 kHz to 100.5 kHz will be severe, so a Hanning window would
be useful in nearly eliminating it. Since there is only one echo frequency to worry about, the
broadening caused by the Hanning window will still allow the echo frequency to be
determined to within one Fourier frequency index, to a resolution of ∆f = 50 Hz. So there is
no need to increase S.
An alternative, a precise number of 100 kHz cycles could be sampled. The much smaller echo
signal would still have spectral leakage, but that would be OK.
2d The maximum signal frequency is 110 kHz at 200 m/s. A sampling frequency of 220 kHz
would allow white noise from 110 kHz to the low pass filter cut off to be aliased below 110
kHz, but this would not seriously reduce the ability to see the frequency of the echo. A better
