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CMSC 411
Computer Systems Architecture
Lecture 7Lecture 7
Basic Pipelining (cont.) &
Instruction Level Parallelism
Alan Sussmanl @
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[email protected]
Administrivia^ •
Questions about HW #1?
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HW #2 on pipelining due next Thursday Feb 26
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HW #2, on pipelining, due next Thursday, Feb. 26
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Start reading Chapter 2 of H&P
CMSC 411 - 7 (from Patterson)
A case study: MIPS R4000^ •
MIPS64 architecture with deeper 8 stage pipeline • MIPS64 architecture, with deeper 8 stage pipeline
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to get higher clock rates
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extra stages come from memory accessest^
h^
i^
ll d
i^
li^
i
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techniques called
superpipelining
CMSC 411 - 7 (from Patterson)
3
MIPS R4000 pipeline stages •^
IF
- 1
st^
half instruction fetch
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PC selection and start instruction cache access
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IS
- 2
nd
half instruction fetch
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complete instruction cache access
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RF
- instruction decode, register fetch, hazard checking, instruction cache hit detection -^
EX
- execution – includes effective address computation, ALU operation, branch targetcomputation and condition evaluation
CMSC 411 - 7 (from Patterson)
MIPS R4000 pipeline (cont.) • DF
st
half data fetch
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st 1 half of data cache access
• DS
nd
half data fetch
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complete data cache access
determine whether data cache access
hit
• WB
- write back for loads and ALU operations
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5
MIPS R4000 pipeline (cont.)^ A 2 cycle load delay
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Might need to restart ADDD’s ALU
MIPS R4000 pipeline (cont.) A 3 cycle branch delay – 1 delay slot + 2 cycle stall for takenbranch (untaken just delay slot)
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7
Forwarding •^
Deeper pipeline increases number of levels offorwarding for ALU operations
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4 possible sources for an ALU bypass – EX/DF, DF/DS, DS/TC,TC/WB
CMSC 411 - 7 (from Patterson)
Pitfalls • Unexpected hazards do occur
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for example, when a branch is taken before a previousi^
t^
ti^
fi^
i h
instruction finishes
- Extensive pipelining can slow a machine down, or
lead to worse cost-performance–
more complex hardware can cause a longer clock cycle,killing the benefits of more pipelining
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Pitfalls (cont.) • A poor compiler can make a good machine look bad
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compiler writers need to understand the architecture in ordertto^ »
optimize efficiently and » avoid hazards b tt
t^
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i^
t^
l^
i^
t^
ti^
th
k^
th
-^
better to eliminate useless instructions, than make them runfaster
CMSC 411 - 7 (from Patterson)
INSTRUCTION-LEVEL PARALLELISM
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15
Outline •^
ILP
•^
Compiler techniques to increase ILP
p
q
•^
Loop Unrolling
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Static Branch Prediction
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Dynamic Branch Prediction
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Overcoming Data Hazards with DynamicSchedulingScheduling
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(Start) Tomasulo Algorithm
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ConclusionConclusion
CMSC 411 - 7 (from Patterson)
Recall from Pipelining^ • Pipeline CPI = Ideal pipeline CPI + Structural Stalls
D t
H
d St ll
C
t^
l St ll
- Data Hazard Stalls + Control Stalls
- Ideal pipeline CPI: measure of the maximum performance
attainable by the implementation
- Structural hazards: HW cannot support this combination of
instructions
- Data hazards: Instruction depends on result of prior
Data hazards: Instruction depends on result of priorinstruction still in the pipeline
- Control hazards: Caused by delay between the fetching of
instructions and decisions about changes in control flowinstructions and decisions about changes in control flow(branches and jumps)
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Instruction Level Parallelism •^
Instruction-Level Parallelism (ILP): overlap theexecution of instructions to improve performance
p^
p
•^
2 approaches to exploit ILP:1)
Rely on hardware to help discover and exploit the parallelismdynamically (e g
Pentium 4 AMD Opteron IBM Power)
and
dynamically (e.g., Pentium 4, AMD Opteron, IBM Power) , and
Rely on software technology to find parallelism, statically atcompile-time (e.g., Itanium 2/IA-64)
CMSC 411 - 7 (from Patterson)
Instruction-Level Parallelism (ILP)
(^
- Basic Block (BB) ILP is quite small
- BB: a straight-line code sequence with no branches in except to the
entry and no branches out except at the exit
- average dynamic branch frequency 15% to 25%
=> 4 to 7 instructions execute between a pair of branches
- Plus instructions in BB likely to depend on each other
across
multiple basic blocks
Simplest: loop level parallelism to exploit parallelism
- Simplest: loop-level parallelism to exploit parallelism
among iterations of a loop. E.g.,
for (i=1; i<=1000; i=i+1)
x[i] = x[i] + y[i];
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Loop-Level Parallelism
p
•^
Exploit loop-level parallelism by “unrolling loop” eitherby1. dynamic via branch prediction or2. static via loop unrolling by compiler(Another way is vectors to be covered later)(Another way is vectors, to be covered later)
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Determining dependences
critical
•^
If 2 instructions are
-^
If^
2 instructions are– parallel, they can execute simultaneously in apipeline of arbitrary depth without causing any stalls
y^
g^
y
(assuming no structural hazards)
- dependent, they are not parallel and must be
t d i
d^
lth
h th
ft^
b
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executed in order, although they may often bepartially overlapped
