ECE 4500/5950 DIGITAL ELECTRONICS
SPRING 2009
Homework Assignment #6
Total: 70 pts.
Due 9:30am, Wednesday, February 25, 2009
Consider the function F = B∙(C’+A) + D’∙A’ using dynamic np-CMOS technology.
That is, break up the function/circuit onto two sections; one being implemented by a n
block and the other one by a p block. Model the circuit using Design Architect and
simulate its dynamic behavior using ELDO and Xelga. Turn in a printout of the circuit
diagram and the simulation results, respectively, along with your comments. No layout is
needed.
1)Verify the correct operation of your circuit and obtain tPHL. Use a 10fF capacitor CL as
a load device. You are to turn in hard copies of your circuit diagram, and simulation
results, respectively. Comment on your results. (50 pts.)
2) By using ELDO and Xelga and your results in Part a, find the highest frequency for
clock (50% duty cycle is assumed). The circuit malfunctions if during precharge
the output voltage doesn't rise above 90% of VDD, or doesn't drop below 10% of VDD
for a low output during evaluation. You are also to find the lowest frequency for clock
for which the circuit still functions. The circuit fails if any of its signals does not
remain within 90% of its expected steady state value before the next clock event is
initiated. Comment on your results. (20 pts.)