ECE 4500/5950 DIGITAL ELECTRONICS
SPRING 2009
Homework Assignment #3
Total: 64 pts.
Due 9:30am, Wednesday, February 4, 2009
Consider the 0.25-micron complementary static CMOS technology used in the Lab
for a 3-input NAND gate with device sizes as follows: PMOS W=4.0μm, L=1.2μm and
NMOS W=2.0μm, L=1.2μm, respectively. Assume that CL = 7fF and VDD = 2.5V. Work
with the parameters given in Table 3-2 on Page 103 of the Text.
Tasks:
a) Obtain analytically the worst-case tPLH and tPHL.. Work with the formulas given on
Page 200 of the Text (5.17, 5.18 and 5.19). You can obtain the λ values from Table 3-2.
(24 pts.)
b) Verify your results in Part a) by modeling and simulating the 3-input NAND gate
above using Design Architect along with ELDO and Xelga. You need to add CL to your
schematics. Turn in a hard copy of your circuit schematic diagram and commented
simulation printouts showing tPLH and tPHL, respectively. Compare your simulation
results with the calculated ones in Part a). (40 pts.)