ECE 4500/5950 DIGITAL ELECTRONICS
SPRING 2009
Homework Assignment #4
Total: 56 pts.
Due 9:30am, Wednesday, February 11, 2009
1. Consider the 0.25-micron complementary static CMOS technology used in the
Lab for a 3-input NAND gate with device sizes as follows: PMOS W=4.0μm,
L=1.2μm and NMOS W=2.0μm, L=1.2μm, respectively. Assume that CL = 7fF and
VDD = 2.5V. Work with the parameters given in Table 3-2 on Page 103 of the Text.
Calculate the dynamic power consumption for this NAND gate. Assume that the
input signal change rate is 250MHz and the probability of the input low-levels are
0.3, 0.5 and 0.7, respectively. (6 pts.)
2. Consider the function F = B∙C’ + D’∙A’ using transmission gates (CMOS pass-
transistor technology). Output signal F should be driven by a level-restorer
complementary CMOS inverter. You may assume that both complemented and un-
complemented signals are available. Model the circuit using Design Architect and
simulate its performance using ELDO and Xelga. Turn in a printout of the circuit
diagram and the simulation results, respectively, along with your comments. No
layout is needed.
Tasks:
a) Verify the correct operation of your circuit. (30 pts.)
b) Obtain tPHL and tPLH through simulation. Use a 6fF capacitor CL as a load device.
(20 pts.)
You are to turn in hard copies of your circuit diagram, and simulation results,
respectively. Comment on your results.