ECE 4500/5950 DIGITAL ELECTRONICS
SPRING 2009
Homework Assignment #5
Total: 60 pts.
Due 9:30am, Wednesday, February 18, 2009
1. Consider the 0.25-micron CMOS technology used in the Lab for a pseudo-NMOS
3-input NOR gate with device sizes as follows: PMOS W=2.0µm, L=10µm and
NMOS W=2.0µm, L=1.2µm, for all NMOS devices, respectively. Assume that CL = 7fF
and VDD = 2.5V. Work with the parameters given in Table 3-2 on Page 103 of the Text.
Tasks:
a) Obtain analytically VOL. (10 pts.)
b) Calculate the worst case static power dissipation for this NOR gate. (10 pts.)
c) Obtain tPLH and the worst case tPHL analytically. (10 pts.)
d) Model the circuit using Design Architect and simulate its performance using ELDO
and Xelga. Use a 7fF capacitor CL as a load device. Obtain VOL, tPLH and the worst case
tPHL by simulation. Turn in a printout of the circuit diagram and the simulation results,
respectively, along with your comments. No layout is needed. (30 pts.)