Energy-Efficient Issue Logic: Reducing Power Consumption in Microprocessors, Slides of Computer Architecture and Organization

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Energy-Effective Issue Logic

Outline

• (^) – – – Introduction Why is Energy Consumption a big issue ?What can be done ?Objectives?
• – – Definitions^ Related worksWhat is issue logic
• Solution^ •^ •^ •^ Register Rename LogicWake-up logicSelection logic
• – Results^ Architectural Design^ •^ •^ Changes made to wake-up logicChanges made to selection logic
  • – ExperimentsConclusions

Objectives

• To show the potential in power savingthrough dynamically reconfiguring the issue

• logicTo maximize the flexibility for a system to

carry out reconfigurations in an effective andefficient manner

• Minimize the impact on performance

Related Works

• • Scaling voltage and frequency dynamicallyProgrammable thermal threshold

• • Disable unused part of the processorReducing cache power

• Smart branch predictions mechanisms

Pipeline organization 2

• pipeline stages

Experimental system

Energy consumption of units in microprocessorfor integer programs

Concerns

• • Concantrate on Issue LogicIssue Logic consist of 2 sub parts

– – Wake-up LogicSelection Logic

Selection Logic

• Chooses instructions for execution from the pool of readyinstructions

Power consumptions

• Instruction queue and its associated issue logic areresponsible for %25 of the total power consumption

• of microprocessorEmpty entries and ready entries wastes power on

• wake-up logicDynamically resize instruction queue to utilize energy

usage

Energy analysis for wake-up logic

• • • Energy consumption of empty entries is on average %74.9 of issue logicEnergy consumption of ready entries is on average %14 of issue logicWake-up logic wastes %89 of total issue logic

Issue Queue Structure

 Non-ready instructions are hidden from theselection logic  power efficient

 Exposure to potential ILP is maximized bymaintaining the size of issue queue at alltimes

 Broadcasting of computed results arerestricted to non-ready instructions only power efficient 

Algorithm

• • Add a bit to reorder bufferDivide instruction queue to smaller portions

• • Set bit zero when instruction dispatchedWhen an instruction is issued this bit is set if it is from theyoungest portion of instruction queue

• • İncrease a counterCheck counter in certain number of cycles which is referred as“ quantum”

• • İf it is smaller than a determined number reduce instruction queue size by 1 portionEvery 5 quantum we increase queue size 1 portion if it is not

at maximum size

Dynamic issue queue Analysis

• • Performance hardly effectedOn average %1.7 IPC lost