Docsity
Log inSign up
Docsity
Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity

Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan

Guidelines and tips
Guidelines and tips
Sell on Docsity
Sell on Docsity
Docsity AI
Docsity AI
Log inSign up

Prepare for your exams

Study with the several resources on Docsity

Find documents

Prepare for your exams with the study notes shared by other students like you on Docsity

Search for your university

Find the specific documents for your university's exams

Docsity AINEW

Summarize your documents, ask them questions, convert them into quizzes and concept maps

Explore questions

Clear up your doubts by reading the answers to questions asked by your fellow students

Earn points to download

Earn points by helping other students or get them with a premium plan

Share documents
download point icon20 Points

For each uploaded document

Answer questions
download point icon5 Points

For each given answer (max 1 per day)

All the ways to get free points
Get points immediately

Choose a premium plan with all the points you need

Study Opportunities

Choose your next study program

Get in touch with the best universities in the world. Search through thousands of universities and official partners

Community

Ask the community

Ask the community for help and clear up your study doubts

Free resources

Our save-the-student-ebooks!

Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors

Concurrent vs Sequential - Computer Science - Lecture Slides, Slides of Computer Science

Amity University - BiharComputer Science

These are the Lecture Slides of Computer Science which includes Bit Adder, Code, Vector, Bcdcarryout, Architecture Behavioral, Component, Signal, Waveform, Logic etc. Key important points are: Concurrent Vs Sequential, Combinational Logic, Circuit Depends, Sequential Logic, Previous Inputs, Concurrent Statement, Operators, Generate Statement, Block Statement, Basic Way of Creating

Typology: Slides

2012/2013

Uploaded on 03/23/2013

dhruv
dhruv 🇮🇳

4.3

(12)

194 documents

1 / 21

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
Concurrent vs Sequential
•Combinational vs Sequential logic
–Combinational logic is that in which the output
of the circuit depends solely on the current
input
–Sequential logic is defined as that in which the
output does depend on previous inputs.
Docsity.com
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14
pf15

Partial preview of the text

Download Concurrent vs Sequential - Computer Science - Lecture Slides and more Slides Computer Science in PDF only on Docsity!

Concurrent vs Sequential

• Combinational vs Sequential logic

– Combinational logic is that in which the output

of the circuit depends solely on the current

input

– Sequential logic is defined as that in which the

output does depend on previous inputs.

Concurrent statement

• Operators

• The WHEN statement

– (When/Else or With/select/when)

– The GENERATE statement

– The BLOCK statement

Operators

Operator

Type

Operators Data types

Logical NOT,AND,NAND, NOR, OR,

XOR,XNOR

Bit, Bit_vector

Std_logic,std_logic_vector

Std_ulogic_vector, std_ulogic

Arithmetic +, -, *, /, ** Integer,signed, unsigned

Comparison =,/=, <, >, <=,>= All above

Shift Sll,srl,sla,sra,rol,ror Bit_vector

Concatenation &, (,,,) Same as above

When (Simple and selected)

• Fundamental concurrent statement

• Syntax

assignment WHEN condition ELSE

assignment WHEN condition ELSE

Circuit of 2:4 decoder

3:8 Decoder

  • entity decodedr38 is
  • Port ( a : in std_logic_vector(2 downto 0);
  • b : out std_logic_vector(7 downto 0);
  • en : in std_logic);
  • end decodedr38;
  • architecture Behavioral of decodedr38 is
  • signal temp : std_logic_vector(7 downto 0);
  • begin
  • temp <= "00000001" when a="000" else
  • "00000010" when a="001" else
  • "00000100" when a="010" else
  • "00001000" when a="011" else
  • "00010000" when a="100" else
  • "00100000" when a="101" else
  • "01000000" when a="110" else
  • "10000000";
  • b <= temp when en='1' else
  • (others => '0');
  • end Behavioral;

5:32 decoder

  • entity decoder532 is
  • Port ( x : in std_logic_vector(4 downto 0);
  • y : out std_logic_vector(31 downto 0));
  • end decoder532;
  • architecture Behavioral of decoder532 is
  • component decoder24 is
  • Port ( din : in std_logic_vector(1 downto 0); -- decoder input
  • dout : out std_logic_vector(3 downto 0)
  • );-- decoder output
  • end component decoder24;
  • component decodedr38 is
  • Port ( a : in std_logic_vector(2 downto 0);
  • b : out std_logic_vector(7 downto 0);
  • en : in std_logic);
  • end component decodedr38;
  • signal temp : std_logic_vector(3 downto 0);

5:32 decoder (cont..)

  • begin
  • u1: decoder24 port map(din(1)=>x(4),din(0)=>x(3),dout(3)=>temp(3),dout(2)=>temp(2),dout(1)=>temp(1),dout(0)=>te mp(0));
  • u2: decodedr38 port map(en=>temp(0),a(2)=>x(2),a(1)=>x(1),a(0)=>x(0),b(7)=>y(7),b(6)=>y(6),b(5)=>y(5),b(4)=>y(4),b (3)=>y(3),b(2)=>y(2),b(1)=>y(1),b(0)=>y(0));
  • u3: decodedr38 port map(en=>temp(1),a(2)=>x(2),a(1)=>x(1),a(0)=>x(0),b(7)=>y(15),b(6)=>y(14),b(5)=>y(13),b(4)=>y( 12),b(3)=>y(11),b(2)=>y(10),b(1)=>y(9),b(0)=>y(8));
  • u4: decodedr38 port map(en=>temp(2),a(2)=>x(2),a(1)=>x(1),a(0)=>x(0),b(7)=>y(23),b(6)=>y(22),b(5)=>y(21),b(4)=>y( 20),b(3)=>y(19),b(2)=>y(18),b(1)=>y(17),b(0)=>y(16));
  • u5: decodedr38 port map(en=>temp(3),a(2)=>x(2),a(1)=>x(1),a(0)=>x(0),b(7)=>y(31),b(6)=>y(30),b(5)=>y(29),b(4)=>y( 28),b(3)=>y(27),b(2)=>y(26),b(1)=>y(25),b(0)=>y(24));
  • end Behavioral;

Example 4: 1 Mux using when

statement

library ieee; use ieee.std_logic_1164.all;

entity mux4_1_when is port (a: in std_logic_vector(3 downto 0); s: in std_logic_vector(1 downto 0); y: out std_logic ); end mux4_1_when;

architecture mux_behave of mux4_1_when is begin y <= a(0) when s = "00" else a(1) when s = "01" else a(2) when s = "10" else a(3); end mux_behave;

Symbol of 2:1 Mux

Example 4:1 mux using with-

select

library ieee; use ieee.std_logic_1164.all;

entity mux4_1_with is port (a: in std_logic_vector(3 downto 0); s: in std_logic_vector(1 downto 0); y: out std_logic ); end mux4_1_with;

architecture mux_behave of mux4_1_with is begin with s select y <= a(0) when "00", a(1) when "01", a(2) when "10", a(3) when others; end mux_behave;

Mux architecture

Truth table of encoder

A3` A2 A1 A0 F1 F

7-segment display