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S205 08/03/
THE MANCHESTER METROPOLITAN UNIVERSITY
FACULTY OF SCIENCE AND ENGINEERING
DEPARTMENT OF ENGINEERING AND TECHNOLOGY
SESSION 2002/
Examination for the BEng (HONS) ELECTRICAL AND ELECTRONIC ENGINEERING FULL-TIME/SANDWICH BEng (HONS) ELECTRONIC ENGINEERING PART-TIME BEng (HONS) MECHATRONICS FULL-TIME/SANDWICH STAGE THREE
UNIT 64ET3105/64EE3006: ELECTRONIC INSTRUMENTATION
Tuesday 13 May 2003
9.30 am to 12.30 pm
Instructions to Candidates
Answer any FOUR questions.
Marks breakdowns for individual questions are shown in parentheses.
You are permitted to use the Faculty Standard calculators as provided.
Rxy ( τ )
τ
τ *Peak of Correlogram
Figure Q1 Basic Cross Correlation flow measuring system
(a) Describe the operation of the Cross Correlation flow measuring system shown in
Figure Q1. What is the significance of the value of τ *, the peak of the Cross
Correlation function, in the measurement of flow? [6]
(b) The system is to be used to measure the mass flow of material through the pipe. What additional sensing, other than sensors A and B, is required? In a practical flow measuring system describe the effect moving the sensor B away from A would have on the mass flow measurement. [4]
(c) Small plastic pellets are pneumatically conveyed through the 8cm-diameter pipe with a maximum velocity of 20 m/sec. The required Velocity Discrimination Factor for the system is 2%. Determine the sample time requirement, suitable sensor spacing and effective range of measurement for the system. [6]
(d) Prove, using Orthagonal functions, that if x ( t )= A cos ω 1 t and
y ( t )= B cos ω 2 t , then the Cross Correlation function
x(t).y(t )dt 0 T
R ( )
T
0
xy τ^ = ∫ +τ = ,
for the condition ω 1 ≠ ω 2. [4]
- An Electrical Capacitance Tomographic ( ECT ) tomographic imaging system is to be used to measure and control the flow of coffee beans to a packaging machine. An 8 sensor array system is to be axially spaced around a non conducting section of pipe.
Flow
Adjustable time Delay τ Multiplier
Integration
L
x ( t ) y ( t )
Sensor A (^) Sensor B
8cm
- A thermistor resistor, R θ , is placed in a Wheatstone bridge configuration as shown in
Figure Q3. The value of resistance varies according to the following equation:
⎥⎦
⎤ ⎢⎣
⎡ θ θ =
3260 R 0. 06 e
where θ is the temperature in degrees Kelvin ( 273+Temperature in degrees C ). The thermistor is used to monitor the temperature in a water jacket of a plastic injection moulding machine. The maximum temperature reached is 50 °C and the output from the bridge has to interfaced to a 12bit , 10 V Analogue to Digital Converter (ADC).
(a) At 50 °C the ADC should have an input level from the instrumentation amplifier of 10V. Design and sketch the circuit diagram of a suitable circuit to provide this 10v input to the ADC. [11]
(b) Determine the minimum Common Mode Rejection Ratio (CMRR) of any amplifiers that may be used in the circuit for the condition that if the common mode voltage from the bridge circuit at 50 °C is to contribute no more than 1 LSB to the output of the instrumentation amplifier. [4]
(c) Determine the theoretical overall CMRR of the instrumentation amplifier given the tolerances of the resistors used in the differential were ± 2 %. State any assumptions made. [5]
Figure Q
8.9k Ω
V o
+2.5V
8.9k Ω
∆ V (^) -
+
∆ V
8.9k Ω
Thermistor R θ
Instrumentation Amplifier
12 bit ,10 V Analogue to Digital Converter
- (a) State the THREE methods of cascading logic counter integrated circuits and state their main merits and limitations. [3]
(b) Show how each form of cascading may be achieved using 74190 decade counters by drawing circuit diagrams showing the main clocking and cascading connections for pairs of these counters. A data sheet for this counter is attached to the exam paper. [6]
(c) This type of counter is to be used as the basis of a 12-hour digital clock, showing minutes and hours only in the range 00.00 to 11.59.
Draw the diagram of a circuit, driven by a 1 MHz crystal clock, which provides pulses at the appropriate rate for the 12-hour clock. Show only the main connections. Briefly describe the circuit. [5]
Draw also a diagram of the counter circuit used to provide the clock display. Do not include the decoders or digital display circuitry. Show only the cascading and clocking connections. Explain briefly the circuit operation. [6]
S205 08/03/04 END
- (a) Explain briefly why the phase detector of a phase locked loop (PLL) must, in addition to phase detection, have a frequency detecting property. [2]
(b) Two popular phase/frequency detectors are:
- the exclusive OR gate; and
- the edge-detecting tristate-output detector.
For EACH of these devices
(i) derive, with reasoning, an expression for its phase detecting transfer function, and [11]
(ii) describe its frequency detecting behaviour. [5]
(c) Hence state briefly how one of these detectors gives a superior PLL performance to that of the other. [2]
- (a) Sketch a diagram of the lock-in-amplifier (LIA) and state the main measurements that it is used to perform. State briefly its advantages in comparison with other methods for similar measurements, and state the limitations of the LIA. [7]
(b) Describe the principle on which the ideal phase sensitive detector operates and illustrate this with diagrams to show the output of an ideal phase sensitive detector to sinusoidal input signals that are:
(i) less than;
(ii) equal to; and
(iii) greater than;
the sinusoidal reference frequency. [5]
(c) Hence describe the characteristics of the filter used with the phase sensitive detector. Illustrate these by sketching and describing appropriate filter output waveforms of a real LIA. [8]
