Cork Institute of Technology
Higher Certificate in Engineering in Electronic Engineering - Stage 1
(National Certificate in Engineering in Electronic Engineering - Stage 1)
(NFQ - Level 6)
Autumn 2005
DIGITAL SYSTEMS
(Time: 3 Hours)
Answer any five questions [20 marks each]
Maximum available marks is 100
Examiners: Mr. J.J. O’Sullivan
Mr. J. Berry
Dr. R. O’Dúbhghaill
Q1 (a) Using any method of your choice, prove that
A
+
A
B
=
A
+
B [5 marks]
(b) Without minimising, draw the logic circuit for the function given by
Z=A+BC +B(C+A) [5 marks]
(c) Minimise as far as possible, the function in (b) above. [5 marks]
(d) Use a K-map to minimise Y
=
ABCD
+
ABD
+
ABCD
+
BCD
+
ABC D [5 marks]
Q2 (a) What is the difference between a level-triggered and an edge-triggered flip-
flop? [3 marks]
(b) Draw a logic symbol and truth table for a positive edge-triggered D-type flip-
flop. [4 marks]
(c) For the circuit in (b), draw a detailed logic diagram and state the feature that
ensures it performs as a D-type circuit. [6 marks]
(d) Draw a diagram to show how a number of D-type flip-flops can be connected
up to store any 4-bit binary number. Briefly explain the action of this circuit. [7 marks]
Q3 (a) In relation to binary counters, state the difference between synchronous and
asynchronous operation. [2 marks]
(b) Draw a detailed logic diagram of a 3-stage synchronous binary counter and
complete a truth table for this circuit. [6 marks]
(c) Describe in detail the operation of the circuit for the first three clock pulses. [4 marks]
(d) Draw a timing diagram for one complete cycle of operation of this counter. [6 marks]
(e) State any advantages this circuit would have over an equivalent asynchronous
circuit. [2 marks]
