SCORE:________ Name:__________________________________________
ECE 4100/6100 Advanced Computer Architecture
Test II – Summer 2004
1. (20 points) A program executes a loop twenty times. If a 2-bit predictor is assigned to
this loop and no aliasing occurs in the BHT with another branch, calculate the
prediction accuracy. Assume all of the predictors are initialized to not taken the 00
state at power up and this is the first time the loop is executed and the first time this
2-bit predictor is accessed after power up. The conditional branch is at the bottom of
the loop.
2 initial incorrect + 1 final = 17/20
Branch Prediction Rate = ___85_________%
What would happen if static branch prediction (like the PIV) was used to initially set the
2-bit predictor to the taken 11 state initially after power up whenever it first sees a
conditional branch that jumps backwards? (Note: This would likely require some extra
hardware in the BHT, but just assume it can do it)
Only final prediction would be incorrect = 19/20
Branch Prediction Rate = ___95_________%
2. (20 points) A single-issue processor has a pipeline CPI of 1.5 and a cache miss rate of
5% per instruction and a 4Ghz clock. A dual-issue version of the processor from another
company has a pipeline CPI of 0.8 and a clock rate of 3Ghz, but with a cache miss rate of
7%. The main memory access time is 10ns for a miss. Compute the MIPS performance of
the two processors including both pipeline and cache CPI effects.
CPIs = 1.5 +.05*10ns/.25ns = 3.5 overall
CPId = .8 +.07*10ns/.33ns = 2.9 overall
4Ghz/3.5 = 1142 MIPS
3Ghz/2.9 = 1034 MIPS
Single-Issue execution rate = ____1142______ MIPS
Dual-Issue execution rate = ____1034______ MIPS
