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Hardware Description Language - Introduction
- HDL is a language that describes the hardware of digital systems in a textual form.
- It resembles a programming language, but is specifically oriented to describing hardware structures and behaviors.
- The main difference with the traditional programming languages is HDL’s representation of extensive parallel operations whereas traditional ones represents mostly serial operations.
- The most common use of a HDL is to provide an alternative to schematics.
HDL – Introduction (2)
- When a language is used for the above purpose (i.e. to provide an alternative to schematics), it is referred to as a structural description in which the language describes an interconnection of components.
- Such a structural description can be used as input to logic simulation just as a schematic is used.
- Models for each of the primitive components are required.
- If an HDL is used, then these models can also be written in the HDL providing a more uniform, portable representation for simulation input.
HDL – Introduction (4)
- As a documentation language, HDL is used to represent and document digital systems in a form that can be read by both humans and computers and is suitable as an exchange language between designers.
- The language content can be stored and retrieved easily and processed by computer software in an efficient manner.
- There are two applications of HDL processing: Simulation and Synthesis
Logic Simulation
- A simulator interprets the HDL description and produces a readable output, such as a timing diagram, that predicts how the hardware will behave before its is actually fabricated.
- Simulation allows the detection of functional errors in a design without having to physically create the circuit.
Logic Simulation
- Logic simulation is a fast, accurate method of analyzing a circuit to see its waveforms
Types of HDL
- There are two standard HDL’s that are supported by IEEE.
- VHDL ( Very-High-Speed Integrated Circuits Hardware Description Language ) - Sometimes referred to as VHSIC HDL, this was developed from an initiative by US. Dept. of Defense.
- Verilog HDL – developed by Cadence Data systems and later transferred to a consortium called Open Verilog International (OVI).
Verilog - Module
- A module is the building block in Verilog.
- It is declared by the keyword module and is always terminated by the keyword endmodule.
- Each statement is terminated with a semicolon, but there is no semi-colon after endmodule.
Verilog – Module (2)
HDL Example
module smpl_circuit(A,B,C,x,y); input A,B,C; output x,y; wire e; and g1(e,A,B); not g2(y,C); or g3(x,e,y); endmodule
Verilog – Module (4)
//Description of circuit with delay module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and # (30) g1(e,A,B); or # (20) g3(x,e,y); not # (10) g2(y,C); endmodule
Verilog – Module (5)
- In order to simulate a circuit with HDL, it is necessary to apply inputs to the circuit for the simulator to generate an output response.
- An HDL description that provides the stimulus to a design is called a test bench.
- The initial statement specifies inputs between the keyword begin and end.
- Initially ABC=000 (A,B and C are each set to 1’b0 (one binary digit with a value 0).
- $finish is a system task.
Verilog – Module (6)
In the above example, cwd is declared as one instance circuit_with_delay. (similar in concept to object<->class relationship)
Verilog – Module (7)
Bitwise operators
- Bitwise NOT : ~
- Bitwise AND: &
- Bitwise OR: |
- Bitwise XOR: ^
- Bitwise XNOR: ~^ or ^~
Verilog – Module (9)
//Circuit specified with Boolean equations
module circuit_bln (x,y,A,B,C,D);
input A,B,C,D; output x,y; assign x = A | (B & C) | (~B & C); assign y = (~B & C) | (B & ~C & ~D);
endmodule
Verilog – Module (10)
User Defined Primitives (UDP):
- The logic gates used in HDL descriptions with keywords and, or ,etc., are defined by the system and are referred to as system primitives.
- The user can create additional primitives by defining them in tabular form.
- These type of circuits are referred to as user-defined primitives.
