Logical Instructions - Computer Architecture - Lecture Slides, Slides of Computer Science

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Computer Architecture

CPSC 321

Overview

• Logical Instructions

• Shifts

Logical Operators

• Two basic logical operators:
  • AND: outputs 1 only if both inputs are 1
  • OR: outputs 1 if at least one input is 1

Logical Operators

• Truth Table: standard table listing all possible combinations of inputs and resultant output for each
• Truth Table for AND and OR

A B AND OR 0 0 0 1 1 0 1 1

• Two basic logical operators:
  • AND: outputs 1 only if both inputs are 1
  • OR: outputs 1 if at least one input is 1

Uses for Logical Operators

• Note that ANDing a bit with 0 produces a 0 at the output while ANDing a bit with 1 produces the original bit.
• This can be used to create a mask.
  • Example:

1011 0110 1010 0100 0011 1101 1001 1010

0000 0000 0000 0000 0000 1111 1111 1111

• The result of ANDing these two is: 0000 0000 0000 0000 0000 1101 1001 1010
• The second bit string in the example is called a mask. It is used to isolate the rightmost 12 bits of the first bit string by masking out the rest of the string (e.g. setting it to all 0s).

Uses for Logical Operators

• Thus, the and operator can be used to set certain portions of a bit string to 0s, while leaving the rest alone. - In particular, if the first bitstring in the above example were in $t0, then the following instruction would mask it: andi $t0,$t0,0xFFF
• Similarly, note that ORing a bit with 1 produces a 1 at the output while ORing a bit with 0 produces the original bit.
• This can be used to force certain bits of a string to 1s.
  • For example, if $t0 contains 0x12345678, then after this instruction: ori$t0, $t0, 0xFFFF
  • $t0 contains 0x1234FFFF (e.g. the high-order 16 bits are untouched, while the low-order 16 bits are forced to 1s).

Shift Instructions (2/3)

• Shift Instruction Syntax:

1 2,3,

• where

1. operation name
2. register that will receive value
3. first operand (register)
4. shift amount (constant <= 32)

MIPS shift instructions:

1. sll (shift left logical): shifts left and fills emptied bits with 0s
2. srl (shift right logical): shifts right and fills emptied bits with 0s
3. sra (shift right arithmetic): shifts right and fills emptied bits by sign extending

Shift Instructions (3/3)

• Example: shift right arith (sra) by 8 bits 0001 0010 0011 0100 0101 0110 0111 1000

 Example: shift right arith (sra) by 8 bits

1001 0010 0011 0100 0101 0110 0111 1000

Uses for Shift Instructions (2/4)

• Could use instead: sll $t0,$t0, srl $t0,$t0,

t 0001 0010 0011 0100 0101 0110 0111 1000 After sll 0101 0110 0111 1000 0000 0000 0000 0000

After srl

Uses for Shift Instructions (3/4)

• In binary: Multiplying by 2 is same as shifting left by 1: 112 x 10 2 = 110 (^2) 10102 x 10 2 = 10100 (^2) Multiplying by 4 is same as shifting left by 2: 11 2 x 100 2 = 1100 (^2) 10102 x 100 2 = 101000 (^2) Multiplying by 2 n^ is same as shifting left by n

The Story so far…

• We introduced numerous MIPS assembly language

instructions.

• We are now familiar with registers and register usage

conventions.

• We know how to use system calls, basic I/O
• We have learned how the stack works
• What is missing?

Practice! Practice! Practice!

What Next?

• We need a more detailed knowledge about the

instruction formats to fully appreciate certain restrictions.

• The functional interface is easy to understand, since it is basically familiar procedural programming
• We need to understand how the computer interprets the instruction, so that we can transition to the discussion of the MIPS hardware architecture

Instruction Word Formats

• Register format
• Immediate format
• Jump format

op-code rs rt rd shamt funct

op-code rs rt immediate value

op-code 26 bit current segment address

6 5 5 16

6 5 5 5 5 6

6 26

Register Format (R-Format)

• Register format
• op: basic operation of instruction
• funct: variant of instruction
• rs: first register source operand
• rt: second register source operand
• rd: register destination operand
• shamt: shift amount

op-code rs rt rd shamt funct 6 5 5 5 5 6