Input Output Module-Assembly Language, Microprocessors and Computer Architecture-Lecture Slides, Slides of Computer Architecture and Organization

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Input/Output Module

• Interface to CPU and Memory
• Interface to one or more peripherals

Generic Model of I/O Module

External Devices

• Human readable —Screen, printer, keyboard
• Machine readable —Monitoring and control
• Communication —Modem —Network Interface Card (NIC)

External Device Block Diagram

I/O Steps

• CPU checks I/O module device status
• I/O module returns status
• If ready, CPU requests data transfer
• I/O module gets data from device
• I/O module transfers data to CPU
• Variations for output, DMA, etc.

I/O Module Diagram

I/O Module Decisions

• Hide or reveal device properties to CPU
• Support multiple or single device
• Control device functions or leave for CPU
• Also O/S decisions —e.g. Unix treats everything it can as a file

Input Output Techniques

• Programmed
• Interrupt driven
• Direct Memory Access (DMA)

I/O Commands

• CPU issues address —Identifies module (& device if >1 per module)
• CPU issues command —Control - telling module what to do - e.g. spin up disk —Test - check status - e.g. power? Error? —Read/Write - Module transfers data via buffer from/to device

Addressing I/O Devices

• Under programmed I/O data transfer is very like memory access (CPU viewpoint)
• Each device given unique identifier
• CPU commands contain identifier (address)

I/O Mapping

• Memory mapped I/O — Devices and memory share an address space — I/O looks just like memory read/write — No special commands for I/O - Large selection of memory access commands available
• Isolated I/O — Separate address spaces — Need I/O or memory select lines — Special commands for I/O - Limited set

Interrupt Driven I/O

• Overcomes CPU waiting
• No repeated CPU checking of device
• I/O module interrupts when ready

Design Issues

• How do you identify the module issuing the interrupt?
• How do you deal with multiple interrupts? —i.e. an interrupt handler being interrupted

Identifying Interrupting Module (1)

• Different line for each module —PC —Limits number of devices
• Software poll —CPU asks each module in turn —Slow

Identifying Interrupting Module (2)

• Daisy Chain or Hardware poll —Interrupt Acknowledge sent down a chain —Module responsible places vector on bus —CPU uses vector to identify handler routine
• Bus Master —Module must claim the bus before it can raise interrupt —e.g. PCI & SCSI

Multiple Interrupts

• Each interrupt line has a priority
• Higher priority lines can interrupt lower priority lines
• If bus mastering only current master can interrupt

ISA Bus Interrupt System

• ISA bus chains two 8259As together
• Link is via interrupt 2
• Gives 15 lines —16 lines less one for link
• IRQ 9 is used to re-route anything trying to use IRQ 2 —Backwards compatibility
• Incorporated in chip set

82C59A Interrupt Controller

Intel 82C55A Programmable Peripheral Interface

Using 82C55A To Control Keyboard/Display

DMA Module Diagram

DMA Operation

• CPU tells DMA controller:- —Read/Write —Device address —Starting address of memory block for data —Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when finished

DMA Transfer Cycle Stealing

• DMA controller takes over bus for a cycle
• Transfer of one word of data
• Not an interrupt —CPU does not switch context
• CPU suspended just before it accesses bus —i.e. before an operand or data fetch or a data write
• Slows down CPU but not as much as CPU doing transfer

Aside

• What effect does caching memory have on DMA?
• Hint: how much are the system buses available?

DMA Configurations (3)

• Separate I/O Bus
• Bus supports all DMA enabled devices
• Each transfer uses bus once —DMA to memory
• CPU is suspended once

I/O Channels

• I/O devices getting more sophisticated
• e.g. 3D graphics cards
• CPU instructs I/O controller to do transfer
• I/O controller does entire transfer
• Improves speed —Takes load off CPU —Dedicated processor is faster

I/O Channel Architecture

Interfacing

• Connecting devices together
• Bit of wire?
• Dedicated processor/memory/buses?
• E.g. FireWire, InfiniBand