Introduction to Code Generation Machine Descriptions - Fall 2004 | EECS 583, Study notes of Electrical and Electronics Engineering

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EECS 583 – Lecture 13 Intro to Code Generation Machine Descriptions

University of Michigan March 1, 2004

• 1 -

Reading Material^ Y

For Today^ » “Machine Description Driven Compilers for EPIC

Processors”, B. Rau, V. Kathail, and S. Aditya, HPTechnical Report, HPL-98-40, 1998.

Y

For next time^ » “Three Architectural Models for Compiler-Controlled

Speculative Execution”, P. Chang, N. Warter, S.Mahlke, W. Chen, and W. Hwu, IEEE Transactionson Computers, Vol. 44, No. 4, April 1995, pp. 481-494.

• 3 -

What Do We Need to Schedule Operations?^ Y

Information about the processor^ »

Number of resources

»^

Which resources are used by each operation

»^

Operation latencies

»^

Operand encoding limitations

»^

For example:^ y

2 issue slots, 1 memory port, 1 adder/multiplier y load = 2 cycles, add = 1 cycle, mpy = 3 cycles; all fully pipelined y Each operand can be register or 6 bit signed literal

Y

Ordering constraints amongst operations^ »

What order defines correct program execution?

»^

Need a precedence graph – flow, anti, output deps^ y

What about memory deps? control deps? Delay slots?

• 4 -

How Do We Schedule?^ Y

When is it legal to schedule an instruction?^ »

Correct execution is maintained

»^

Resources not oversubscribed

Y

Given multiple operations that can be scheduled, how doyou pick the best one?^ »

How do you know it is the best one?^ y

What about a good guess? y Does it matter, just pick one at random?

»^

Are decisions final?, or is this an iterative process?

Y

How do we keep track of resources that are busy/free^ »

Need a reservation table^ y

Matrix (resources x time)

• 6 -

Compiler Code Generation – 2

nd

try

Y^

Map optimized “machine-independent” assembly to finalassembly code

Y^

Virtual

Æ

physical binding

»^

Cannot do this all at once, toomany decisions!! »^

Do slowly »^

Each step refines the bindingby restricting previouschoices

Y^

Schedule both before and afterregister allocation^ »

Initial scheduling is free ofreal processor registerconstraints »^

nd 2 phase required due to spill code

code selection, literal handling prepass operation binding

scheduling

register allocation and spill code insertion

postpass scheduling

code emission

• 7 -

Why Not Schedule After Register Allocation?

physical registers

virtual registers r1 = load(r10) r2 = load(r11) r3 = r1 + 4 r4 = r1 – r12 r5 = r2 + r4 r6 = r5 + r3 r7 = load(r13) r8 = r7 * 23 store (r8, r6)

R1 = load(R1) R2 = load(R2) R5 = R1 + 4 R1 = R1 – R3 R2 = R2 + R1 R2 = R2 + R5 R5 = load(R4) R5 = R5 * 23 store (R5, R2)

Too many artificial ordering constraints!!!!

• 9 -

The 6 Step Program (cont)^ Y

4. Register allocation^ »

Assign physical registers

»^

Bind each access-equivalent register to a specific physicalregister

»^

Introduce additional code to spill registers to memory

Y

5. Postpass scheduling^ »

A second pass of scheduling to handle spill code

»^

Resource assignments from first pass are ignored

»^

But, registers are physical, so less code motion freedom

Y

6. Code emission^ »

Convert “fully qualified” operations into real assembly

»^

A translator basically

»^

Assembler converts this assembly to machine code

Y

Focus for now on 3, 4, 5, assume 1, 2, 6 are not needed

• 10 -

Machine Information^ Y

Each step of code generation requires knowledge of themachine^ »

Hard code it? – used to be common practice

»^

Retargetability, then cannot

Y

What does the code generator need to know about thetarget processor?^ »

Structural information?^ y

No

»^

For each opcode^ y

What registers can be accessed as each of its operands y Other operand encoding limitations

»^

Operation latencies^ y

Read inputs, write outputs

»^

Resources utilized^ y

Which ones, when

• 12 -

IO Format^ Y

Registers, register files^ »

Number, width, static or rotating

»^

Read-only (hardwired 0) or read-write

Y

Operation^ »

Number of source/dests

»^

Predicated or not

»^

For each source/dest/pred^ y

What register file(s) can be read/written y Literals, if so, how big

Multicluster machine example:

ADD_W.

gpr1, gpr1 : gpr

ADD_W_L.

gpr1, lit6 : gpr

ADD_W.

gpr2, gpr2 : gpr

• 13 -

Latency Information^ Y

Multiply takes 3 cycles^ »

No, not that simple!!!

Y^

Differential input/outputlatencies^ »

Earliest read latency for eachsource operand »^

Latest read latency for eachsource operand »^

Earliest write latency for eachdestination operand »^

Latest write latency for eachdestination operand

Y^

Why all this?^ »

Unexpected events may makeoperands arrive late or beproduced early

Y^

Compound op: part may finishearly or start late

Y^

Instruction re-execution by^ »

Exception handlers »^

Interupt handlers

Y^

Ex: mpyadd(d1, d2, s1, s2, s3)^ »

d1 = s1 * s2, d2 = d1 + s

s

s2 d

s

E/L

s1: 0/

s2: 0/

s3: 2/

d1: 2/3 d2: 2/

d

• 15 -

Branch Latency^ Y

Time relative to the initiation time of a branch at whichthe target of the branch is initiated

Y

What about branch prediction?^ »

Can reduce branch latency

»^

But, may not make it 1

Y

We will assume branch latency is 1 for this class (ie nodelay slots!)

0: branch 1: xxx 2: yyy 3: target

Example:

branch latency = k (3) delay slots = k – 1 (2) Note xxx and yyy are multiOps

• 16 -

Resources^ Y

A machine resource

is any aspect of the target processor

for which over-subscription is possible if not explicitlymanaged by the compiler^ »

Scheduler must pick conflict free combinations

Y

3 kinds of machine resources^ »

Hardware resources

are hardware entities that would be occupied

or used during the execution of an opcode^ y

Integer ALUS, pipeline stages, register ports, busses, etc.

»^

Abstract resources

are conceptual entities that are used to model

operation conflicts or sharing constraints that do not directlycorrespond to any hardware resource^ y

Sharing an instruction field

»^

Counted resources

are identical resources such that k are required

to do something^ y

Any 2 input busses

• 18 -

Now, Lets Get Back to Scheduling…^ Y

Scheduling constraints^ »

What limits the operations that can be concurrently executed orreordered?

»^

Processor resources – modeled by mdes

»^

Dependences between operations^ y

Data, memory, control

Y

Processor resources^ »

Manage using resource usage map (RU_map)

»^

When each resource will be used by already scheduled ops

»^

Considering an operation at time t^ y

See if each resource in reservation table is free

»^

Schedule an operation at time t^ y

Update RU_map by marking resources used by op busy

• 19 -

Data Dependences^ Y

Data dependences^ »

If 2 operations access the same register, they are dependent

»^

However, only keep dependences to most recentproducer/consumer as other edges are redundant

»^

Types of data dependences

Output

Anti

Flow

r1 = r2 + r3r1 = r4 * 6

r1 = r2 + r3r2 = r5 * 6

r1 = r2 + r3r4 = r1 * 6