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High Performance Computing

Lecture 27

2

Memory Hierarchy

 CPU registers

 few in number (typically 16/32/128)

 subcycle access time (nsec)

 Cache memory

 on-chip memory

 10’s of KBytes (to a few MBytes)

 access time of a few cycles

 Main memory

 100’s of MBytes storage (to a few GBytes)

 access time several 10’s of cycles

 Secondary storage (like disk)

 100’s of GBytes storage (to a few TBytes)

 access time of msecs

4

Why Hierarchy?

 Consider hierarchy in a business organization

 Purpose: Right quantity of right quality human

resource to achieve the required performance

 Realities of storage: Size-speed tradeoff

 Disks: large storage, slow speed, low cost

 Silicon memory: high cost for large, fast memory

 So, cost effective memory hierarchy with

 Small amount of very fast memory

 Affordable amount of medium speed memory

 Huge amounts of very slow memory

5

How Cache Works

CPU

address

Main Memory

Cache Memory

Case 1: Cache contains the data

Same: Hit

tag index offset

Case 2: Data not in cache

Not Same: Miss

7

The 4 Qs of Cache Organization

1. Where can a memory block be placed in the

cache? (Block Placement)

 Direct mapped, Set Associative

2. How is a block identified in the cache?

 Tag, valid bit, tag checking hardware

3. What is the replacement policy used?

 LRU, FIFO, Random …

4. What happens on writes to the cache?

 Cache Hit: When is main memory updated?

 Cache Miss: What happens on a write miss?

8

Cache

Main Memory

Block

Notation

( Depicted as a block of size 4 bytes

for convenience in drawing )

8 block cache memory and 16 block main memory

10

Identifying Block in DM Cache

Assume 32 bit address space, 16 KB cache, 32byte

cache block size.

Number of cache blocks = 16KB / 32B = 512

Index field: to identify the unique cache block

log

2

512 = 9 bits

Offset field: to identify the desired byte in cache block

log

2

32 = 5 bits

Tag field: to identify which memory block is currently

in this cache block

Tag Index Offset

(remaining 18 bits)

11

Accessing Block in DM Cache

Tag V D

AND

Cache Hit

Data

Tag

18 bits

Index

9 bits

Offset

5 bits