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Microprocessor and assembly language
Typology: Assignments
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Explain the following Intel microprocessor architectures briefly (with diagrams)
8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology. It has the following configuration: 8-bit data bus 16-bit address bus, which can address up to 64KB A 16-bit program counter A 16-bit stack pointer Six 8-bit registers arranged in pairs: BC, DE, HL Requires +5V supply to operate at 3.2 MHZ single phase clock 8085 Microprocessor –Functional Units 8085 consists of the following functional units: Accumulator: It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is connected to internal data bus & ALU. Arithmetic and logic unit: As the name suggests, it performs arithmetic and logical operations like Addition, Subtraction, AND, OR, etc. on 8-bit data.
As the name suggests it controls the interrupts during a process. When a microprocessor is executing a main program and whenever an interrupt occurs, the microprocessor shifts the control from the main program to process the incoming request. After the request is completed, the control goes back to the main program. There are 5 interrupt signals in 8085 microprocessors: INTR, RST 7.5, RST 6.5, RST 5.5, TRAP. Diagram: We have tried to depict the architecture of 8085 with this following diagram: Address bus : A15-A8, it carries the most significant 8-bits of memory/IO address. Data bus :
AD7-AD0, it carries the least significant 8-bit address and data bus. Control and status signals : These signals are used to identify the nature of operation. There are 3 control signal and 3 status signals. Three control signals are RD, WR & ALE. RD: This signal indicates that the selected IO or memory device is to be read and is ready for accepting data available on the data bus. WR: This signal indicates that the data on the data bus is to be written into a selected memory or IO location. ALE: It is a positive going pulse generated when a new operation is started by the microprocessor. When the pulse goes high, it indicates address. When the pulse goes down it indicates data.
80386 microprocessor that was designed by Intel in October 1985 and was an upgraded version of 80286 microprocessor. 80386 Microprocessor is a 32-bit processor that holds the ability to carry out 32-bit operation in one cycle. It has data and address bus of 32-bit each. Thus has the ability to address 4 GB (or 232 ) of physical memory.
It allows system software to use features such as virtual memory, paging and safe multi-tasking designed to increase an operating system control over application software. It begins executing instructions in real mode. Virtual mode: In virtual mode , the overall memory of 80386 can be divided into various virtual machines Allows the execution of real mode application that are incapable of running directly in protected mode. All of them acts as a separate computer with 8086 microprocessor. Architecture of 80386 Microprocessor: Basically it has 6 functional units which are as follows: Bus Interface Unit: The bus interface unit or BIU holds a 32-bit bidirectional data bus as well as 32-bit address bus. The BIU connects the peripheral devices through the memory unit and also
Code Pre fetch Unit: This unit fetches the instructions stored in the memory by making use of system buses. Whenever the system generates a need for an instruction then the code pre fetch unit
fetches that instruction from the memory and stores it in 16-byte pre fetch queue. It is to be noted here that, code prefetching holds lower priority than data transferring. Instruction Decode Unit: Instructions in the memory are stored in the form of bits. So, this unit decodes the instructions stored in the pre fetch queue. Execution Unit: The execution unit controls the execution of the decoded instructions. This unit has a 32- bit ALU, that performs the operation over 32-bit data in one cycle. Also, it consists of 8 general purpose as well as 8 special purpose registers. These are used for data handling and calculation of offset address. Memory Management Unit: This unit has two separate units within it. These are i. Segmentation Unit: The segmentation unit plays a vital role in the 80836 microprocessor. It offers protection mechanism in order to protect the code or data present in the memory from application programs. It gives 4 level protection to the data or code present in the memory. Every information in the memory is assigned a privilege level from PL0 to PL3. Here, PL0 holds the highest priority and PL3 holds the lowest priority. ii. Paging Unit:
independent integral integers processors. This allows Pentium to execute two instructions per clock cycle. Another feature of Pentium is jump prediction technology which speeds up the execution of program loops. The Pentium also provides an internal floating point instruction to handle floating point data. These features continued to be the core of success for the intel family of microprocessors. It may also allow the Pentium to replace some of the instruction set of computer that currently executes one instruction per clock cycle. Control Unit: Control unit interprets the instruction word and microcode entry point given to it by Instruction Decode Unit. This unit also control the integer pipeline and floating point sequences also it handles interrupts, exceptions and breakpoints. The pipeline is further divided into two instruction pipelines U-pipeline V-pipeline Pentium Registers: Four 32 bit registers are categorized as following Four 32 bit register (EAX, EBX, ECX, EDX) Four 16 bit register (AX, BX, CX, DX) Eight 8 bit register (AH, AL, BH, BL, CH, CL, DH, DL)
ECX for count in loop instructions Pre fetch Buffers: Four prefetch buffers work as two independent pairs within the processor. Instructions are placed in one of buffers when prefetched from cache. These buffer sends a pair of instructions to instruction decoder which then forwards it to instruction decode unit. Instruction decode unit further occurs in two stages. Decode1 (D1): - it checks whether instructions can be paired or not. Decode2 (D2): - calculates the address of memory resident operands. E-Flags: Flags never change for any data transfer or program control operation while some flags are also used to control features found in the microprocessor. Following are the flag bits with brief description of function. A: (auxiliary carry) holds the carry after addition or the borrow after subtraction between bit positions 3 and 4 of the result. C: carry the after addition or borrows after subtraction. Also indicates error conditions. D: selects increment or decrement mode of the SI or DI registers. O: overflow indicates the result has exceeded the capacity of the machine. P: count of once in a number expressed as even or odd. S: sign flag stands for the arithmetic sign of a flag. T: The trap flag enables trapping through an on-chip debugging feature.
parallel. The Core 2 Duo, which was introduced on July 27 2006, is the direct successor of the Core Duo. Each core is based on the Pentium M micro architecture. Key Features: 64 bit support. Dual core processor with shared level 2 cache. Execute Disable Bit. Partially Intel Virtualization Technology (VT) Socket M (starting from Santa Rosa socket P) 291 million transistors. Performance: The performance of the Core 2 Duo processor in comparison with its direct competitor, the AMD Turion 64 X2, is very good. The Core 2 Duo beats the AMD Turion 64 X with the same clock rate in virtually all applications (on average by 15%). The energy consumption is similar in both processors. In comparison with the predecessor Core Duo, the Core 2 Duo is about 10% faster and consumes a bit more energy Specifications: The Core 2 Duo processors are produced in 65 nm (and later in 45nm), contain 14 stages pipelines and 2-4 MB level 2 cache (depending on the model). The features of the Core 2 Duo are
x86 Architecture : The Intel Core 2 Duo uses the x instruction set, which was introduced in 1978 with the 8086/8088 processor. Furthermore it supports the multimedia extension MMX, SSE2, SSE3 and SSE Dual core technology: Two processor cores run with the same frequency in the same processor building block and share the level 2 cache as well as the front side bus (FSB). Execute disable bit: Prevents security problems through buffer overflows, if the operation system supports it and if it is activated. Every core can execute four complete commands simultaneously. Shorter idle times, improved data transfer and faster out-of-order command execution lead to better usage of the pipeline and as a result to higher performance. Shorter idle times, improved data transfer and faster out-of-order command execution lead to better usage of the pipeline and as a result to higher performance One 128-Bit SSE command is now output per clock cycle. The Intel VT offers hardware support for virtual systems on one computer (use of several isolated operation systems at the same time e.g. through Xen or VMWare). Beware, not all models support VT Support of 64 bit wide words in the CPU. This means the processor can handle 64 bit data packets. The Intel Core 2 Duo supports the AMD64 extension (licensed), through which 32 and
Another new feature is the dynamically overclocking of the core , called "Dynamic Acceleration". If only one core is used, it can be dynamically overclocked, while the second core stays in the energy saving C3-modus.
The Core i7 is a CPU series manufactured by Intel aimed at high-range computers. We will present a series of quick reference tables for you to compare the main differences between all models released to date. By the way, the correct name of this line of processors is “Core i7,” Not “Intel i7”. With the release of the Nehalem microarchitecture in November 2008, Intel introduced a new naming scheme for its Core processors. There are three variants, Core i3, Core i and Core i7, but the names no longer correspond to specific technical features like the number of cores. Instead, the brand is now divided from low-level (i3), through mid-range (i5) to high-end performance (i7), which correspond to three, four and five stars in Intel's Intel Processor Rating following on from the entry-level Celeron (one star) and Pentium (two stars) processors. Common features of all Nehalem based processors include an integrated DDR3 memory controller as well as Quick Path Interconnect or PCI Express and Direct Media Interface on the processor replacing the aging quad-pumped Front Side Bus used in all earlier Core processors. All these processors have 256 KB L2 cache per core, plus up to 12 MB
shared L3 cache. Because of the new I/O interconnect, chipsets and mainboards from previous generations can no longer be used with Nehalem-based processors. Generation 1: Nehalem microarchitecture (1st generation) "Bloomfield" (45 nm) All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Enhanced Intel speed step Technology (EIST), Intel 64 , XD bit (an NX bit implementation), Intel VT-x, Hyper-threading, Turbo Boost, Smart Cache_._ FSB has been replaced with QPI. Transistors: 731 million Die size: 263 mm² Steppings: C0, D "Lynnfield" (45 nm) All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, Enhanced Intel SpeedStep Technology (EIST), Intel 64 , XD bit (an NX bit implementation), TXT, Intel VT-x, Intel VT-d, Hyper-threading, Turbo Boost, Smart Cache. Core i7-875K features an unlocked multiplier and does not support Intel TXT and Intel VT-d.[1] FSB has been replaced with DMI.
Intel introduced the Core i7 name with the Nehalem-based Bloomfield Quad-core processor in late 2008. In 2009 new Core i7 models based on the Lynnfield (Nehalem- based) desktop quad-core processor and the Clarksfield (Nehalem-based) quad-core mobile were added, and models based on the Arrandale dual-core mobile processor (also Nehalem-based) were added in January 2010. The first six-core processor in the Core lineup is the Nehalem-based Gulftown, which was launched on March 16, 2010. Both the regular Core i7 and the Extreme Edition are advertised as five stars in the Intel Processor Rating. In each of the first three microarchitecture generations of the brand, Core i7 has family members using two distinct system-level architectures, and therefore two distinct sockets (for example, LGA 1156 and LGA 1366 with Nehalem). In each generation, the highest- performing Core i7 processors use the same socket and QPI-based architecture as the medium-end Xeon processors of that generation, while lower-performing Core i processors use the same socket and PCIe/DMI/FDI architecture as the Core i5. "Core i7" is a successor to the Intel Core 2 brand. Intel representatives stated that they intended the moniker Core i7 to help consumers decide which processor to purchase as Intel releases newer Nehalem-based products in the future.
The 8085 and 8086 are both different versions of microprocessors produced by Intel in the ’70s. They are the most common available microprocessors.
Here we will compare 8086 microprocessor architecture with 8085. The 8085 pronounced as “Eighty-Eighty-five” is an 8-bit microprocessor first introduced by Intel in the year 1976. Its data bus is 8-bit long which means it can process 8-bit of data at a time. Its address bus is 16-bit wide which means it can access 216 different memory locations. Since each memory location contains a byte (8-bit) of data, the maximum accessible memory capacity of 8085 becomes 216 or 64KB. It is equipped with an on-chip internal oscillator of 3 MHz the reason it has an 8-bit data bus is that it has an 8-bit ALU (Arithmetic Logic Unit). Its ALU is capable of the operations such as, add, subtract, increase, decrease, compare, shift, complement, ADD, OR, X-OR The 8086 is a 16-bit microprocessor introduced by Intel in 1976. It is the enhanced version of the 8085 microprocessors. It has a 16-bit data bus with a 16-bit ALU. The address bus is a 20 bit long; therefore, the accessible memory capacity of 8086 microprocessor is a 220 Bytes or 1MB.It is available in various versions with a clock frequency of 5MHz, 8MHz and 10MHz.It has a 16-bit ALU capable of performing all the operations of 8085's ALU and also the operation of Multiplication and Division. Main Differences between 8085 and 8086 Microprocessor: 8085 Microprocessor 8086 Microprocessor It is an 8-bit microprocessor. It is a 16-bit microprocessor. It has an 8-bit wide data bus. It has 16-bit wide data bus. It can address 2^8 = 256 I/O ports. It can address 2^16 = 65,536 I/O ports. It has 16-bit wide address bus. It has 20-bit wide address bus. It has an 8-bit ALU (Arithmetic Logic Unit). It has a 16-bit ALU. It can process an 8-bit of data in one machine cycle. It can process 16-bit of data in one machine cycle The maximum accessible memory (RAM) it can access is 2^16 = 64KB. The maximum accessible memory of 8086 is 220 = 1MB. Its memory is not segmented. Its memory is segmented into four blocks of 64KB.
