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memory and 64Terabytes of Virtual memory. ▻ It has pipeline architecture which allows simultaneous instruction fetching, decoding, and executing and memory ...
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Two versions of 80386 are commonly available:
32 bit processor, it has 32 bit ALU which allows to process 32 bit data at a time. 32 bit address bus, therefore it can access 4 GB physical memory and 64 Terabytes of Virtual memory. It has pipeline architecture which allows simultaneous instruction fetching, decoding, and executing and memory management. Because of instruction pipelining higher bus bandwidth & on chip address translation mechanism, the average execution time has been significantly reduced. It allows user to switch between different OS such as DOS and UNIX Operates in Real, Protected and Virtual 8086 mode.
a) Execution Unit : Reads the instruction instruction queue and execute the instruction. from the Consists of three subunits : control, data and protection test unit I) Control Unit: It contains microcode and special hardware allows processor to reduce time required for execution of multiply and divide instruction. It also speeds the effective address calculation. II) Data Unit: Responsible for data operations requested by the control unit. It contains ALU, eight 32 bit general purpose registers and 64 bit barrel shifter. The barrel shifter is used for multiple bit shifts in one clock. Thus it increases the speed of all shift and rotate operations.
III) Protection Test Unit: checks for segmentation violations under the control of the microcode. b) Instruction Decode Unit : Takes instruction byte from the code prefetch queue and translates them in to microcode. The decoded instructions are then stored in the instruction queue.
a) Segmentation Unit: Translate logical address to linear addresses at the request of execution unit. Compares the effective address for the length limit specified in the segment descriptor. Adds the segment base and the effective address to generate linear address. Before calculation of linear address it also checks access rights. It provides a 4 level protection mechanism for protecting and isolating the system code and data from those of the application program
ii)It send address, data and control signals to communicate with memory and I/O devices iii)It controls the interface to external bus masters and coprocessors. iv)It also provides the address relocation facility. Instruction Prefetch Unit Fetches sequentially the instruction byte stream from the memory. It uses bus control unit to fetch instruction bytes when it is not performing bus cycles. These prefetched instruction bytes are stored in 16 bytes code queue. When jump or call instructions are executed, the contents of the prefetched and decode queues are cleared out
