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Test Benches - Computer Science - Lecture Slides, Slides of Computer Science

Amity University - Bihar Computer Science

These are the Lecture Slides of Computer Science which includes Bit Adder, Code, Vector, Bcdcarryout, Architecture Behavioral, Component, Signal, Waveform, Logic etc. Key important points are: Test Benches, Design By Simulation, Test Bench Model, Timing Model, Simulation Cycle, Digital Hardware, Start Simulation, Update Signals, Execute Processes, End Simulation

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Test Benches

•Testing a design by simulation

•Use a test bench model

–an architecture body that includes an instance

of the design under test

–applies sequences of test values to inputs

–monitors values on output signals

•either using simulator

•or with a process that verifies correct operation

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Download Test Benches - Computer Science - Lecture Slides and more Slides Computer Science in PDF only on Docsity!

Test Benches

• Testing a design by simulation

• Use a test bench model

– an architecture body that includes an instance

of the design under test

– applies sequences of test values to inputs

– monitors values on output signals

• either using simulator

• or with a process that verifies correct operation

Test Bench Example

entity test_bench is end entity test_bench;

architecture test_reg4 of test_bench is

signal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;

begin

dut : entity work.reg4(behav) port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 ); stimulus : process is begin d0 <= ’1’; d1 <= ’1’; d2 <= ’1’; d3 <= ’1’; wait for 20 ns; en <= ’0’; clk <= ’0’; wait for 20 ns; en <= ’1’; wait for 20 ns; clk <= ’1’; wait for 20 ns; d0 <= ’0’; d1 <= ’0’; d2 <= ’0’; d3 <= ’0’; wait for 20 ns; en <= ’0’; wait for 20 ns; … wait ; end process stimulus;

end architecture test_reg4;

What Is The VHDL Test Bench (TB)?

VHDL test bench (TB) is a piece of VHDL code, which

purpose is to verify the functional correctness of HDL

model.

The main objectives of TB is to:

Instantiate the design under test (DUT)
Generate stimulus waveforms for DUT
Generate reference outputs and compare them with the

outputs of DUT

Automatically provide a pass or fail indication

Test bench is a part of the circuits specification.

Its a good idea to design the test bench before the

DUT, why?

Stimulus and Response

Three ways how TB can generate the stimulus:

Generate them “on-the-fly”
Read vectors stored as constants in an array
Read vectors stored in a separate system file

Response is produced in the test bench.

Response can be stored into file for further processing.

Example:

Stimulus can be generated with Matlab and TB feeds it

into DUT.

DUT generates the response and TB stores it into file.
Result can be compared to Matlab simulations.

Simple Test Bench
- Only the DUT is instantiated into test bench.
- Stimulus is generated inside the test bench
- Poor reusability.
- Suitable only for relatively simple designs.

Test Benches - Computer Science - Lecture Slides, Slides of Computer Science

Related documents

Partial preview of the text

Download Test Benches - Computer Science - Lecture Slides and more Slides Computer Science in PDF only on Docsity!

Test Benches

• Testing a design by simulation

• Use a test bench model

– an architecture body that includes an instance

of the design under test

– applies sequences of test values to inputs

– monitors values on output signals

• either using simulator

• or with a process that verifies correct operation

Test Bench Example

What Is The VHDL Test Bench (TB)?

VHDL test bench (TB) is a piece of VHDL code, which

purpose is to verify the functional correctness of HDL

model.

The main objectives of TB is to:

outputs of DUT

Test bench is a part of the circuits specification.

Its a good idea to design the test bench before the

DUT, why?

Stimulus and Response

Three ways how TB can generate the stimulus:

Response is produced in the test bench.

Response can be stored into file for further processing.

Example:

into DUT.