Test Benches - Sequential Logic Design - Lecture Slides, Slides of Digital Logic Design and Programming

Download Test Benches - Sequential Logic Design - Lecture Slides and more Slides Digital Logic Design and Programming in PDF only on Docsity!

Sequential Logic Design

Lecture

• Agenda
  1. VHDL : Test Benches
• Announcements
  1. HW # 6 due
  2. HW #7 assigned
  3. Next Test 1 review

• Test Benches
  • We need to stimulate our designs in order to test their functionality
  • Stimulus in a real system is from an external source, not from our design
  • We need a method to test our designs that is not part of the design itself
  • This is called a "Test Bench"
  • Test Benches are VHDL entity/architectures with the following:
    • We instantiate the design to be tested using components
    • We call these instantiations "Unit Under Test" (UUT) or "Device Under Test".
    • The entity has no ports
    • We create a stimulus generator within the architecture
    • We can use reporting features to monitor the expected outputs

entity Test_Mux is end entity Test_Mux; -- the test bench entity has no ports

architecture Test_Mux_arch of Test_Mux is

signal In1_TB, In2_TB : STD_LOGIC; -- setup internal Test Signals signal Sel_TB : STD_LOGIC; -- give descriptive names to make signal Out_TB : STD_LOGIC; -- apparent they are test signals

component Mux_2to1 -- declare any used components port (A, B, Sel : in STD_LOGIC; Y : out STD_LOGIC); end component;

begin

UUT : Mux_2to1 -- instantiate the design to test port map ( A => In1_TB, B => In2_TB, Sel => Sel_TB, Y => Out_TB);

STIM : process -- create process to generate stimulus begin In1_TB <= '0'; In2_TB <= '0'; Sel_TB <= '0' wait for 10ns -- we can use wait In1_TB <= '0'; In2_TB <= '1'; Sel_TB <= '0' wait for 10ns -- statements to control In1_TB <= '1'; In2_TB <= '0'; Sel_TB <= '0' wait for 10ns -- the speed of the stim

: : : In1_TB <= '1'; In2_TB <= '1'; Sel_TB <= '1' wait for 10ns -- end with a wait…

end process STIM;

end architecture Test_Mux_2to1;

• Report
  • the keyword "report" will always print a string
  • this is good for outputting the process of a test
  • Severity levels are also reported

ex) report "Beginning the MUX test" severity NOTE;

A<='0'; B<='0'; wait for 10ns; assert (Z='1') report "Failed test 00" severity ERROR;