Operators - Sequential Logic Design - Lecture Slides, Slides of Digital Logic Design and Programming

Download Operators - Sequential Logic Design - Lecture Slides and more Slides Digital Logic Design and Programming in PDF only on Docsity!

Lecture

• Agenda
  1. VHDL : Operators
  2. VHDL : Signal Assignments
• Announcements
  1. HW #4 assigned

Sequential Logic Design

• VHDL Operators
  • Data types define both "values" and "operators"
  • There are "Pre-Determined" data types

Pre-determined = Built-In = STANDARD Package

• We can add additional types/operators by including other Packages
• We'll first start with the STANDARD Package that comes with VHDL

• Numerical Operators
  • works on types INTEGER, REAL
  • the types of the input operands must be the same

• "addition"

• "subtraction"

• "multiplication" / "division" mod "modulus" rem "remainder" abs "absolute value" ** "exponential"

ex) Can we make an adder circuit yet?

A,B : in BIT_VECTOR (7 downto 0) Z : out BIT_VECTOR (7 downto 0)

Z <= A + B;

• Relational Operators
  • used to compare objects
  • objects must be of same type
  • Output is always BOOLEAN (TRUE, FALSE)
  • works on types: BOOLEAN, BIT, BIT_VECTOR, CHARACTER, INTEGER, REAL, TIME, STRING

= "equal" /= "not equal" < "less than" <= "less than or equal"

"greater than" = "greater than or equal"

• Concatenation Operator
  • combines objects of same type into an array
  • the order is preserved

& "concatenate"

ex) New_Bus <= ( Bus1(7:4) & Bus2(3:0) )

• STD_LOGIC_1164 Operators
  • To expand the data types we have in VHDL, we include the IEEE Package "STD_LOGIC_1164"
  • This gives us the data types:

STD_LOGIC STD_LOGIC_VECTOR

• This gives us all of the necessary operators for these types

Logical Numerical Relational Shift

Delayed Assignments

• Delay Modeling
  • VHDL allows us to include timing information into assignment statements
  • this gives us the ability to model real world gate delay
  • we use the keyword "after" in our assignment followed by a time operand.

Ex) B <= not A after 2ns;

• VHDL has two types of timing models that allow more accurate representation of real gates

1. Inertial Delay (default)

2. Transport Delay

Delayed Assignments

• Inertial Delay
  • if the input has two edge transitions in less time than the inertial delay, the pulse is ignored

said another way…

• if the input pulse width is smaller than the delay, it is ignored
• this models the behavior of trying to charge up the gate capacitance of a MOSFET

ex) B <= A after 5ns;

any pulses less than 5ns in width are ignored.