Architecture - Sequential Logic Design - Lecture Slides, Slides of Digital Logic Design and Programming

Download Architecture - Sequential Logic Design - Lecture Slides and more Slides Digital Logic Design and Programming in PDF only on Docsity!

Lecture

• Agenda
  1. VHDL - Architecture
  2. VHDL - Packages
• Announcements
  1. HW #3 assigned

Sequential Logic Design

VHDL Constructs

• Systems in VHDL
  • Systems need to have two things described

1. Interface (I/O, Ports…)

2) Behavior ( Functionality, Structure)

• In VHDL, we do this using entity and architecture

Entity - used to describe a system's interface

• we call the Inputs and Outputs "Ports"
• creating this in VHDL is called an "Entity Declaration"

Architecture - used to describe a system's behavior (or structure)

• separate from an entity
• an architecture must be tied to an entity
• creating this in VHDL is called an "Architecture Definition"

adder.vhd entity declaration

architecture definition

VHDL Architecture

• Architecture Details
  • an architecture is always associated with an entity (in the same file too)
  • an architecture definition must possess the following:

1. architecture-name - user selected, different from entity

• we usually give something descriptive (adder_arch, and2_arch)
• some companies like to use "behavior", "structural" as the names

2. entity-name - the name of the entity that this architecture is associated with

• must already be declared before compile

3. optional items… - types

• signals : internal connections within the architecture
• constants
• functions : calling predefined blocks
• procedures : calling predefined blocks
• components : calling predefined blocks

4. end architecture - keywords to signify the end of the definition

• we follow this by the architecture name and ";"

VHDL Architecture

• Architecture Syntax

architecture architecture-name of entity-name is

type… signal… constant… function… procedure… component…

begin

…behavior or structure

end architecture architecture-name ;

NOTE: - the keywords are architecture, of, is, type…component, begin, end

• there is a ";" at the end of the last line

VHDL Packages

• VHDL is a "Strong Type Cast" language…
  • this means that assignments between different data types are not allowed.
  • this means that operators must be defined for a given data types.
  • this becomes important when we think about synthesis

ex) string + real = ???

• can we add a string to a real?
• what is a "string" in HW?
• what is a "real" in HW?
• VHDL has built-in features:

1. Data Types
2. Operators

• built-in is also called "pre-defined"

VHDL Packages

• Pre-defined Functionality

ex) there is a built in addition operator for integers

integer + integer = integer

• the built-in operator "+" works for "integers" only
• it doesn't work for "bits" as is
• Adding on Functionality
• VHDL allows us to define our own data types and operators
• a set of types, operators, functions, procedures… is called a "Package"
• A set of packages are kept in a "Library"

VHDL Packages

• Common IEEE Packages
  • in the IEEE library, there are common Packages that we use:

STD_LOGIC_

STD_LOGIC_ARITH

STD_LOGIC_SIGNED

Ex) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL;

• libraries are defined before the entity declaration

VHDL Design

• Let's Put it all together now…

library IEEE; -- package use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL;

entity and2 is -- entity declaration

port (In1, In2 : in STD_LOGIC; Out1 : out STD_LOGIC);

end entity and2;

architecture and2_arch of and2 is -- architecture definition

begin Out1 <= In1 and In2;

end architecture and2_arch;