ECE 3550 DIGITAL DESIGN
FALL 2008
Homework Assignment #6
Total: 80 pts.
Due 11:30am, Monday, October 27, 2008
The logic diagram of a synchronous sequential circuit is given on Page 2. The signals at
the outputs of the JK flip-flops change on the falling edge of the signal CLOCK.You
should assume that inputs X1and X2will change on the rising edge of CLOCK.
Furthermore, for drawing a timing diagram for the circuit you may assume that the flip-
flops and gates exhibit no propagation delays. However, each flip-flop may perform just
one state transition at each clock.
Tasks
1. Give the flip-flop input functions and the output functions, respectively. (6 pts.)
2. Give the combined circuit excitation and output table. (30 pts.)
3. Give the assigned state table. (16 pts.)
4. Draw a state transition diagram for the circuit. (4 pts.)
5. Complete the timing diagram for CLOCK pulses 1-8. Prior to the rising edge of
CLOCK pulse #1 the state of the circuit is as follows: y1y2=01, X1X2=10, and Z1Z2=11.
The X1X2input string (starting on the rising edge of CLOCK pulse #1) is 11, 00, 10,
10, 00, 00, 11, and 01. (24 pts.)