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Main points of this exam paper are: Vertical Line, Unusual State of Affairs, Computer Engineering, Transparent Latch, Signals Are Applied, Vertical Line, Transparent Latches, ImplementToggle Cell, Transparent Latches, Computer Engineering
Typology: Exams
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4 problems, 5 pages Exam Two 24 October 2007
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate the pages of the exam. For maximum credit, show your work. Good Luck!
Your Name ( please print ) ________________________________________________
1 2 3 4 total
4 problems, 5 pages Exam Two 24 October 2007
Problem 1 (4 parts, 34 points) An unusual state of affairs
Part A (8 points) Implement a transparent latch using only inverters and pass gates. Label the inputs In and En , and output Out.
Part B (8 points) Assume the following signals are applied to your register. Draw the output signal Out. Draw a vertical line where In is sampled. Draw crosshatch where Out is unknown.
Part C (8 points) Implement a toggle cell using only transparent latches, an inverter, a two to one mux, and a 2-input AND gate. Use an icon for the transparent latches. Label the inputs TE , Clr (^) , Φ 1 , Φ 2 and the output Out.
4 problems, 5 pages Exam Two 24 October 2007
Problem 3 (3 parts, 28 points) Representations
Part A (10 points) Convert the following notations:
decimal notation binary notation 395
octal notation hexadecimal notation
Part B (12 points) For the 30 bit representations below, determine the most negative value, most positive value, and step size (difference between sequential values). All answers should be expressed in decimal notation. Fractions (e.g., 3/16ths) may be used. All signed representations are two’s complement.
representation most negative value most positive value step size unsigned integer (30 bits). (0 bits) signed fixed-point (25 bits). (5 bits) signed fixed-point (20 bits). (10 bits) signed fixed-point (15 bits). (15 bits)
Part C (6 points) An 18 bit single precision floating point representation has a ten bit mantissa field, a seven bit exponent field, and one sign bit.
4 problems, 5 pages Exam Two 24 October 2007
Problem 4 (3 parts, 22 points) Building Blocks
Part A (7 points) Consider the following circuit below. Determine its input priority.
Part B (7 points) Derive a simplified expression for O 0.
O 0 =
Part C (8 points) Complete the truth table for a 1 to 4 demux implemented using pass gates. Do not implement the demux.
In S 1 S 0 O 0 O 1 O 2 O (^3) A 0 0
A 0 1
A 1 0
A 1 1
