Virtual Memory - Introduction to Computer Systems - Lecture Slides, Slides of Computer System Design and Architecture

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Virtual Memory

Objectives

Be able to explain the rationale for VM

Be able to explain how VM is implemented

Be able to translate virtual addresses to

physical addresses

Be able to explain how VM benefits fork() and

exec()

Problem 1: How Does Everything Fit?

64-bit addresses:

16 Exabyte (16 billion GB!) Physical main memory:

Tens or Hundreds of Gigabytes

?

And there are many processes ….

Problem 2: Memory Management

Physical main memory

What goes where?

stack

heap

.text

.data

Process 1

Process 2

Process 3

Process n

x

Solution: Indirection

“All problems in computer science can be solved by another level of indirection... Except for the problem of too many layers of indirection.” – David Wheeler

Each process gets its own private memory space

Solves the previous problems

Physical memory

Virtual memory

Virtual memory

Process 1

Process n

mapping

Address Spaces

Virtual address space: Set of N = 2n^ virtual addresses

{0, 1, 2, 3, …, N-1}

Physical address space: Set of M = 2m^ physical addresses

{0, 1, 2, 3, …, M-1}

Clear distinction between data (bytes) and their

attributes (addresses)

Each object can have multiple addresses

Every byte in main memory:

one physical address, one (or more) virtual addresses

A System Using Virtual Addressing

Used in all modern desktops, laptops,

workstations

M-1:

Main memory

MMU

Physical address (PA)

Data word

CPU

Virtual address (VA)

CPU Chip

Why Virtual Memory (VM)?

Efficient use of limited main memory (RAM)

 Use RAM as a cache for parts of a virtual address space

• some non-cached parts stored on disk
• some (unallocated) non-cached parts stored nowhere

 Keep only active areas of virtual address space in memory

• transfer data back and forth as needed

Simplifies memory management for programmers

 Each process gets the same full, private linear address space

Isolates address spaces

 One process can’t interfere with another’s memory

• because they operate in different address spaces

 User process cannot access privileged information

• different sections of address spaces have different permissions

VM as a Tool for Caching

Virtual memory: array of N = 2n^ contiguous bytes

 think of the array (allocated part) as being stored on disk

Physical main memory (DRAM) = cache for allocated virtual

memory

Basic unit: page; size = 2p

PP 2m-p-

Physical memory

Empty

Empty

Uncached

VP 0 VP 1

VP 2n-p-

Virtual memory

Unallocated Cached Uncached Unallocated Cached Uncached

PP 0 PP 1

Empty Cached

0

2 n-

2 m-

0

Virtual pages (VP's) stored on disk

Physical pages (PP's) cached in DRAM

 Disk

Memory Hierarchy: Core 2 Duo

Disk

Main

Memory

L

unified cache

L

I-cache

L

D-cache

CPU Reg

Throughput: 16 B/cycle 8 B/cycle 2 B/cycle 1 B/30 cycles

Latency: 3 cycles 14 cycles 100 cycles millions

~4 MB

32 KB

~4 GB ~500 GB

Not drawn to scale

L1/L2 cache: 64 B blocks

Miss penalty (latency): 30x

Miss penalty (latency): 10,000x

A System Using Virtual Addressing

Used in all modern desktops, laptops,

workstations

M-1:

Main memory

MMU

Physical address (PA)

Data word

CPU

Virtual address (VA)

CPU Chip

Address Translation: Page Tables

A page table is an array of page table entries (PTEs)

that maps virtual pages to physical pages. Here: 8 VPs

 Per-process kernel data structure in DRAM

null

null

Memory resident page table (DRAM)

Physical memory (DRAM)

VP 7 VP 4

Virtual memory (disk)

Valid 0 1 0 1 0 1

0

1

Physical page number or disk address PTE 0

PTE 7

PP 0

VP 2

VP 1

PP 3

VP 1 VP 2

VP 4 VP 6 VP 7

VP 3

Page Hit

Page hit: reference to VM word that is in

physical memory

null

null

Memory resident page table (DRAM)

Physical memory (DRAM)

VP 7 VP 4

Virtual memory (disk)

Valid 0 1 0 1 0 1

0

1

Physical page number or disk address PTE 0

PTE 7

PP 0

VP 2

VP 1

PP 3

VP 1 VP 2

VP 4 VP 6 VP 7

VP 3

Virtual address

Page Miss

Page miss: reference to VM word that is not in

physical memory

null

null

Memory resident page table (DRAM)

Physical memory (DRAM)

VP 7 VP 4

Virtual memory (disk)

Valid 0 1 0 1 0 1

0

1

Physical page number or disk address PTE 0

PTE 7

PP 0

VP 2

VP 1

PP 3

VP 1 VP 2

VP 4 VP 6 VP 7

VP 3

Virtual address