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ATMEGA328 datasheet manual, Manuais, Projetos, Pesquisas de Engenharia Elétrica

datasheet do atmega328, manual

Tipologia: Manuais, Projetos, Pesquisas

2020

Compartilhado em 25/02/2020

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Features
High Performance, Low Power AVR® 8-Bit Microcontroller
Advanced RISC Architecture
131 Powerful Instructions – Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 20 MIPS Throughput at 20 MHz
On-chip 2-cycle Multiplier
High Endurance Non-volatile Memory Segments
4/8/16/32K Bytes of In-System Self-Programmable Flash progam memory
(ATmega48P/88P/168P/328P)
256/512/512/1K Bytes EEPROM (ATmega48P/88P/168P/328P)
512/1K/1K/2K Bytes Internal SRAM (ATmega48P/88P/168P/328P)
Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
Data retention: 20 years at 85°C/100 years at 25°C(1)
Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
Programming Lock for Software Security
Peripheral Features
Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
Real Time Counter with Separate Oscillator
Six PWM Channels
8-channel 10-bit ADC in TQFP and QFN/MLF package
Temperature Measurement
6-channel 10-bit ADC in PDIP Package
Temperature Measurement
Programmable Serial USART
Master/Slave SPI Serial Interface
Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Interrupt and Wake-up on Pin Change
Special Microcontroller Features
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
I/O and Packages
23 Programmable I/O Lines
28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
1.8 - 5.5V for ATmega48P/88P/168PV
2.7 - 5.5V for ATmega48P/88P/168P
1.8 - 5.5V for ATmega328P
Temperature Range:
–-40
°C to 85°C
Speed Grade:
ATmega48P/88P/168PV: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
ATmega48P/88P/168P: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
ATmega328P: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Low Power Consumption at 1 MHz, 1.8V, 25°C for ATmega48P/88P/168P:
Active Mode: 0.3 mA
Power-down Mode: 0.1 µA
Power-save Mode: 0.8 µA (Including 32 kHz RTC)
8-bit
Microcontroller
with 4/8/16/32K
Bytes In-System
Programmable
Flash
ATmega48P/V
ATmega88P/V
ATmega168P/V
ATmega328P
Preliminary
Summary
Rev. 8025FS–AVR–08/08
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14
pf15
pf16
pf17
pf18
pf19
pf1a

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Features

• High Performance, Low Power AVR ®^ 8-Bit Microcontroller

• Advanced RISC Architecture

**- 131 Powerful Instructions – Most Single Clock Cycle Execution

  • 32 x 8 General Purpose Working Registers
  • Fully Static Operation
  • Up to 20 MIPS Throughput at 20 MHz
  • On-chip 2-cycle Multiplier**

• High Endurance Non-volatile Memory Segments

- 4/8/16/32K Bytes of In-System Self-Programmable Flash progam memory

(ATmega48P/88P/168P/328P)

**- 256/512/512/1K Bytes EEPROM (ATmega48P/88P/168P/328P)

  • 512/1K/1K/2K Bytes Internal SRAM (ATmega48P/88P/168P/328P)
  • Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
  • Data retention: 20 years at 85°C/100 years at 25°C** (1) - Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

- Programming Lock for Software Security

• Peripheral Features

**- Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

  • One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture**

Mode

**- Real Time Counter with Separate Oscillator

  • Six PWM Channels
  • 8-channel 10-bit ADC in TQFP and QFN/MLF package**

Temperature Measurement

- 6-channel 10-bit ADC in PDIP Package

Temperature Measurement

**- Programmable Serial USART

  • Master/Slave SPI Serial Interface
  • Byte-oriented 2-wire Serial Interface (Philips I**^2 **C compatible)
  • Programmable Watchdog Timer with Separate On-chip Oscillator
  • On-chip Analog Comparator
  • Interrupt and Wake-up on Pin Change**

• Special Microcontroller Features

**- Power-on Reset and Programmable Brown-out Detection

  • Internal Calibrated Oscillator
  • External and Internal Interrupt Sources
  • Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,**

and Extended Standby

• I/O and Packages

**- 23 Programmable I/O Lines

  • 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF**

• Operating Voltage:

**- 1.8 - 5.5V for ATmega48P/88P/168PV

  • 2.7 - 5.5V for ATmega48P/88P/168P
  • 1.8 - 5.5V for ATmega328P**

• Temperature Range:

– -40 ° C to 85 ° C

• Speed Grade:

**- ATmega48P/88P/168PV: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

  • ATmega48P/88P/168P: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
  • ATmega328P: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V**

• Low Power Consumption at 1 MHz, 1.8V, 25 ° C for ATmega48P/88P/168P:

**- Active Mode: 0.3 mA

  • Power-down Mode: 0.1 μA
  • Power-save Mode: 0.8 μA (Including 32 kHz RTC)**

8-bit

Microcontroller

with 4/8/16/32K

Bytes In-System

Programmable

Flash

ATmega48P/V

ATmega88P/V

ATmega168P/V

ATmega328P

Preliminary

Summary

Rev. 8025FS–AVR–08/

ATmega48P/88P/168P/328P

1. Pin Configurations

Figure 1-1. Pinout ATmega48P/88P/168P/328P

(PCINT19/OC2B/INT1) PD

(PCINT20/XCK/T0) PD

GND

VCC

GND

VCC

(PCINT6/XTAL1/TOSC1) PB

(PCINT7/XTAL2/TOSC2) PB

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

ADC

GND

AREF

ADC

AVCC

PB5 (SCK/PCINT5)

(PCINT21/OC0B/T1) PD

(PCINT22/OC0A/AIN0) PD

(PCINT23/AIN1) PD

(PCINT0/CLKO/ICP1) PB

(PCINT1/OC1A) PB

(PCINT2/SS/OC1B) PB

(PCINT3/OC2A/MOSI) PB

(PCINT4/MISO) PB

PD2 (INT0/PCINT18)PD1 (TXD/PCINT17)PD0 (RXD/PCINT16)PC6 (RESET/PCINT14)PC5 (ADC5/SCL/PCINT13)PC4 (ADC4/SDA/PCINT12)PC3 (ADC3/PCINT11)PC2 (ADC2/PCINT10)

TQFP Top View

(PCINT14/RESET) PC

(PCINT16/RXD) PD

(PCINT17/TXD) PD

(PCINT18/INT0) PD

(PCINT19/OC2B/INT1) PD

(PCINT20/XCK/T0) PD

VCC

GND

(PCINT6/XTAL1/TOSC1) PB

(PCINT7/XTAL2/TOSC2) PB

(PCINT21/OC0B/T1) PD

(PCINT22/OC0A/AIN0) PD

(PCINT23/AIN1) PD

(PCINT0/CLKO/ICP1) PB

PC5 (ADC5/SCL/PCINT13)

PC4 (ADC4/SDA/PCINT12)

PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

GND

AREF

AVCC

PB5 (SCK/PCINT5)

PB4 (MISO/PCINT4)

PB3 (MOSI/OC2A/PCINT3)

PB2 (SS/OC1B/PCINT2)

PB1 (OC1A/PCINT1)

PDIP

32 MLF Top View

(PCINT19/OC2B/INT1) PD

(PCINT20/XCK/T0) PD

GND

VCC

GND

VCC

(PCINT6/XTAL1/TOSC1) PB

(PCINT7/XTAL2/TOSC2) PB

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

ADC

GND

AREF

ADC

AVCC

PB5 (SCK/PCINT5)

(PCINT21/OC0B/T1) PD

(PCINT22/OC0A/AIN0) PD

(PCINT23/AIN1) PD

(PCINT0/CLKO/ICP1) PB

(PCINT1/OC1A) PB

(PCINT2/SS/OC1B) PB

(PCINT3/OC2A/MOSI) PB

(PCINT4/MISO) PB

PD2 (INT0/PCINT18)PD1 (TXD/PCINT17)PD0 (RXD/PCINT16)PC6 (RESET/PCINT14)PC5 (ADC5/SCL/PCINT13)PC4 (ADC4/SDA/PCINT12)PC3 (ADC3/PCINT11)PC2 (ADC2/PCINT10)

NOTE: Bottom pad should be soldered to ground.

28 MLF Top View

(PCINT19/OC2B/INT1) PD

(PCINT20/XCK/T0) PD

VCC

GND

(PCINT6/XTAL1/TOSC1) PB

(PCINT7/XTAL2/TOSC2) PB

(PCINT21/OC0B/T1) PD

(PCINT22/OC0A/AIN0) PD

(PCINT23/AIN1) PD

(PCINT0/CLKO/ICP1) PB

(PCINT1/OC1A) PB

(PCINT2/SS/OC1B) PB

(PCINT3/OC2A/MOSI) PB

(PCINT4/MISO) PB

PD2 (INT0/PCINT18)PD1 (TXD/PCINT17)PD0 (RXD/PCINT16)PC6 (RESET/PCINT14)PC5 (ADC5/SCL/PCINT13)PC4 (ADC4/SDA/PCINT12)PC3 (ADC3/PCINT11)

PC2 (ADC2/PCINT10)

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

GND

AREF

AVCC

PB5 (SCK/PCINT5)

NOTE: Bottom pad should be soldered to ground.

ATmega48P/88P/168P/328P

The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page

1.1.7 AV CC

AV CC is the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally

connected to VCC , even if the ADC is not used. If the ADC is used, it should be connected to VCC

through a low-pass filter. Note that PC6..4 use digital supply voltage, V CC.

1.1.8 AREF

AREF is the analog reference pin for the A/D Converter.

1.1.9 ADC7:6 (TQFP and QFN/MLF Package Only)

In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.

These pins are powered from the analog supply and serve as 10-bit ADC channels.

1.2 Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology. Min and Max values

will be available after the device is characterized.

ATmega48P/88P/168P/328P

2. Overview

The ATmega48P/88P/168P/328P is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega48P/88P/168P/328P achieves throughputs approaching 1 MIPS per MHz allowing the

system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

PORT D (8) PORT B (8) PORT C (7)

USART 0

8bit T/C 2

8bit T/C 0 16bit T/C 1 A/D Conv.

Internal

Bandgap

Analog

Comp.

SPI TWI

Flash SRAM

EEPROM

Watchdog

Oscillator

Watchdog

Timer

Oscillator

Circuits /

Clock

Generation

Power

Supervision

POR / BOD &

RESET

GND VCC

PROGRAM

LOGIC

debugWIRE

GND

AREF

AVCC

DATABUS

PD[0..7] PB[0..7] PC[0..6] ADC[6..7]

RESET

XTAL[1..2]

CPU

ATmega48P/88P/168P/328P

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

Note: 1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

ATmega48P/88P/168P/328P

5. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page (0xFF) Reserved – – – – – – – – (0xFE) Reserved – – – – – – – – (0xFD) Reserved – – – – – – – – (0xFC) Reserved – – – – – – – – (0xFB) Reserved – – – – – – – – (0xFA) Reserved – – – – – – – – (0xF9) Reserved – – – – – – – – (0xF8) Reserved – – – – – – – – (0xF7) Reserved – – – – – – – – (0xF6) Reserved – – – – – – – – (0xF5) Reserved – – – – – – – – (0xF4) Reserved – – – – – – – – (0xF3) Reserved – – – – – – – – (0xF2) Reserved – – – – – – – – (0xF1) Reserved – – – – – – – – (0xF0) Reserved – – – – – – – – (0xEF) Reserved – – – – – – – – (0xEE) Reserved – – – – – – – – (0xED) Reserved – – – – – – – – (0xEC) Reserved – – – – – – – – (0xEB) Reserved – – – – – – – – (0xEA) Reserved – – – – – – – – (0xE9) Reserved – – – – – – – – (0xE8) Reserved – – – – – – – – (0xE7) Reserved – – – – – – – – (0xE6) Reserved – – – – – – – – (0xE5) Reserved – – – – – – – – (0xE4) Reserved – – – – – – – – (0xE3) Reserved – – – – – – – – (0xE2) Reserved – – – – – – – – (0xE1) Reserved – – – – – – – – (0xE0) Reserved – – – – – – – – (0xDF) Reserved – – – – – – – – (0xDE) Reserved – – – – – – – – (0xDD) Reserved – – – – – – – – (0xDC) Reserved – – – – – – – – (0xDB) Reserved – – – – – – – – (0xDA) Reserved – – – – – – – – (0xD9) Reserved – – – – – – – – (0xD8) Reserved – – – – – – – – (0xD7) Reserved – – – – – – – – (0xD6) Reserved – – – – – – – – (0xD5) Reserved – – – – – – – – (0xD4) Reserved – – – – – – – – (0xD3) Reserved – – – – – – – – (0xD2) Reserved – – – – – – – – (0xD1) Reserved – – – – – – – – (0xD0) Reserved – – – – – – – – (0xCF) Reserved – – – – – – – – (0xCE) Reserved – – – – – – – – (0xCD) Reserved – – – – – – – – (0xCC) Reserved – – – – – – – – (0xCB) Reserved – – – – – – – – (0xCA) Reserved – – – – – – – – (0xC9) Reserved – – – – – – – – (0xC8) Reserved – – – – – – – – (0xC7) Reserved – – – – – – – – (0xC6) UDR0 USART I/O Data Register 195 (0xC5) UBRR0H USART Baud Rate Register High 199 (0xC4) UBRR0L USART Baud Rate Register Low 199 (0xC3) Reserved – – – – – – – – (0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 /UDORD0 UCSZ00 / UCPHA0 UCPOL0 197/ (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 196 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 195

ATmega48P/88P/168P/328P

(0x7D) Reserved – – – – – – – – (0x7C) ADMUX REFS1 REFS0 ADLAR – MUX3 MUX2 MUX1 MUX0 263 (0x7B) ADCSRB – ACME – – – ADTS2 ADTS1 ADTS0 266 (0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 264 (0x79) ADCH ADC Data Register High byte 266 (0x78) ADCL ADC Data Register Low byte 266 (0x77) Reserved – – – – – – – – (0x76) Reserved – – – – – – – – (0x75) Reserved – – – – – – – – (0x74) Reserved – – – – – – – – (0x73) Reserved – – – – – – – – (0x72) Reserved – – – – – – – – (0x71) Reserved – – – – – – – – (0x70) TIMSK2 – – – – – OCIE2B OCIE2A TOIE2 163 (0x6F) TIMSK1 – – ICIE1 – – OCIE1B OCIE1A TOIE1 139 (0x6E) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 111 (0x6D) PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 74 (0x6C) PCMSK1 – PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 74 (0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 74 (0x6A) Reserved – – – – – – – – (0x69) EICRA – – – – ISC11 ISC10 ISC01 ISC00 71 (0x68) PCICR – – – – – PCIE2 PCIE1 PCIE (0x67) Reserved – – – – – – – – (0x66) OSCCAL Oscillator Calibration Register 37 (0x65) Reserved – – – – – – – – (0x64) PRR PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI PRUSART0 PRADC 42 (0x63) Reserved – – – – – – – – (0x62) Reserved – – – – – – – – (0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 37 (0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 54 0x3F (0x5F) SREG I T H S V N Z C 9 0x3E (0x5E) SPH – – – – – (SP10) 5.^ SP9 SP8 12 0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 12 0x3C (0x5C) Reserved – – – – – – – – 0x3B (0x5B) Reserved – – – – – – – – 0x3A (0x5A) Reserved – – – – – – – – 0x39 (0x59) Reserved – – – – – – – – 0x38 (0x58) Reserved – – – – – – – – 0x37 (0x57) SPMCSR SPMIE (RWWSB)5.^ – (RWWSRE) 5.^ BLBSET PGWRT PGERS SELFPRGEN 293 0x36 (0x56) Reserved – – – – – – – – 0x35 (0x55) MCUCR – BODS BODSE PUD – – IVSEL IVCE 44/68/ 0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF 54 0x33 (0x53) SMCR – – – – SM2 SM1 SM0 SE 40 0x32 (0x52) Reserved – – – – – – – – 0x31 (0x51) Reserved – – – – – – – – 0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 248 0x2F (0x4F) Reserved – – – – – – – – 0x2E (0x4E) SPDR SPI Data Register 175 0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X 174 0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 173 0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 25 0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 25 0x29 (0x49) Reserved – – – – – – – – 0x28 (0x48) OCR0B Timer/Counter0 Output Compare Register B 0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A 0x26 (0x46) TCNT0 Timer/Counter0 (8-bit) 0x25 (0x45) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS 0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM 0x23 (0x43) GTCCR TSM – – – – – PSRASY PSRSYNC 143/ 0x22 (0x42) EEARH (EEPROM Address Register High Byte) 5.^21 0x21 (0x41) EEARL EEPROM Address Register Low Byte 21 0x20 (0x40) EEDR EEPROM Data Register 21 0x1F (0x3F) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE 21 0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 25 0x1D (0x3D) EIMSK – – – – – – INT1 INT0 72 0x1C (0x3C) EIFR – – – – – – INTF1 INTF0 72

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

ATmega48P/88P/168P/328P

Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega48P/88P/168P/328P is a complex microcontroller with more peripheral units than can be supported within the 64

location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only

the ST/STS/STD and LD/LDS/LDD instructions can be used.

5. Only valid for ATmega88P/168P.

0x1B (0x3B) PCIFR – – – – – PCIF2 PCIF1 PCIF 0x1A (0x3A) Reserved – – – – – – – – 0x19 (0x39) Reserved – – – – – – – – 0x18 (0x38) Reserved – – – – – – – – 0x17 (0x37) TIFR2 – – – – – OCF2B OCF2A TOV2 163 0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 140 0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV 0x14 (0x34) Reserved – – – – – – – – 0x13 (0x33) Reserved – – – – – – – – 0x12 (0x32) Reserved – – – – – – – – 0x11 (0x31) Reserved – – – – – – – – 0x10 (0x30) Reserved – – – – – – – – 0x0F (0x2F) Reserved – – – – – – – – 0x0E (0x2E) Reserved – – – – – – – – 0x0D (0x2D) Reserved – – – – – – – – 0x0C (0x2C) Reserved – – – – – – – – 0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 93 0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 93 0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 93 0x08 (0x28) PORTC – PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 92 0x07 (0x27) DDRC – DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 92 0x06 (0x26) PINC – PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 92 0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 92 0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 92 0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 92 0x02 (0x22) Reserved – – – – – – – – 0x01 (0x21) Reserved – – – – – – – – 0x0 (0x20) Reserved – – – – – – – –

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

13

  • ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ARITHMETIC AND LOGIC INSTRUCTIONS
  • ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H
  • ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S
  • SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H
  • SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H
  • SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H
  • SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H
  • SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S
  • AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V
  • ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V
  • OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V
  • ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V
  • EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V
  • COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V
  • NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H
  • SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V
  • CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V
  • INC Rd Increment Rd ← Rd + 1 Z,N,V
  • DEC Rd Decrement Rd ← Rd − 1 Z,N,V
  • TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V
  • CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V
  • SER Rd Set Register Rd ← 0xFF None
  • MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C
  • MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C
  • MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C
  • FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C
  • FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C
  • FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C
  • RJMP k Relative Jump PC ← PC + k + 1 None BRANCH INSTRUCTIONS
  • IJMP Indirect Jump to (Z) PC ← Z None
  • JMP (1) k Direct Jump PC ← k None
  • RCALL k Relative Subroutine Call PC ← PC + k + 1 None
  • ICALL Indirect Call to (Z) PC ← Z None
  • CALL (1) k Direct Subroutine Call PC ← k None
  • RET Subroutine Return PC ← STACK None
  • RETI Interrupt Return PC ← STACK I
  • CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/
  • CP Rd,Rr Compare Rd − Rr Z, N,V,C,H
  • CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H
  • CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H
  • SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/
  • SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/
  • SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/
  • SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/
  • BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/
  • BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/
  • BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/
  • BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/
  • BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/
  • BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/
  • BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/
  • BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/
  • BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/
  • BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/
  • BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/
  • BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/
  • BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/
  • BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/
  • BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/
  • BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/
  • BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/
  • BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/
  • BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/ ATmega48P/88P/168P/328P
  • BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/
  • SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None BIT AND BIT-TEST INSTRUCTIONS
  • CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None
  • LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V
  • LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V
  • ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V
  • ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V
  • ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V
  • SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None
  • BSET s Flag Set SREG(s) ← 1 SREG(s)
  • BCLR s Flag Clear SREG(s) ← 0 SREG(s)
  • BST Rr, b Bit Store from Register to T T ← Rr(b) T
  • BLD Rd, b Bit load from T to Register Rd(b) ← T None
  • SEC Set Carry C ← 1 C
  • CLC Clear Carry C ← 0 C
  • SEN Set Negative Flag N ← 1 N
  • CLN Clear Negative Flag N ← 0 N
  • SEZ Set Zero Flag Z ← 1 Z
  • CLZ Clear Zero Flag Z ← 0 Z
  • SEI Global Interrupt Enable I ← 1 I
  • CLI Global Interrupt Disable I ← 0 I
  • SES Set Signed Test Flag S ← 1 S
  • CLS Clear Signed Test Flag S ← 0 S
  • SEV Set Twos Complement Overflow. V ← 1 V
  • CLV Clear Twos Complement Overflow V ← 0 V
  • SET Set T in SREG T ← 1 T
  • CLT Clear T in SREG T ← 0 T
  • SEH Set Half Carry Flag in SREG H ← 1 H
  • CLH Clear Half Carry Flag in SREG H ← 0 H
  • MOV Rd, Rr Move Between Registers Rd ← Rr None DATA TRANSFER INSTRUCTIONS
  • MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None
  • LDI Rd, K Load Immediate Rd ← K None
  • LD Rd, X Load Indirect Rd ← (X) None
  • LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None
  • LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None
  • LD Rd, Y Load Indirect Rd ← (Y) None
  • LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None
  • LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None
  • LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None
  • LD Rd, Z Load Indirect Rd ← (Z) None
  • LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None
  • LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None
  • LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None
  • LDS Rd, k Load Direct from SRAM Rd ← (k) None
  • ST X, Rr Store Indirect (X) ← Rr None
  • ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None
  • ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None
  • ST Y, Rr Store Indirect (Y) ← Rr None
  • ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None
  • ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None
  • STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None
  • ST Z, Rr Store Indirect (Z) ← Rr None
  • ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None
  • ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None
  • STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None
  • STS k, Rr Store Direct to SRAM (k) ← Rr None
  • LPM Load Program Memory R0 ← (Z) None
  • LPM Rd, Z Load Program Memory Rd ← (Z) None
  • LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None
  • IN Rd, P In Port Rd ← P None SPM Store Program Memory (Z) ← R1:R0 None -
  • OUT P, Rr Out Port P ← Rr None
  • PUSH Rr Push Register on Stack STACK ← Rr None

ATmega48P/88P/168P/328P

Note: 1. These instructions are only available in ATmega168P and ATmega328P.

POP Rd Pop Register from Stack Rd ← STACK None 2 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A

Mnemonics Operands Description Operation Flags #Clocks

ATmega48P/88P/168P/328P

7.2 ATmega88P

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 28-1 on page 317 and Figure 28-2 on page 318.

Speed (MHz) Power Supply Ordering Code (2)^ Package (1)^ Operational Range

10 (3)^ 1.8 - 5.

ATmega88PV-10AU

ATmega88PV-10MU

ATmega88PV-10PU

32A

32M1-A

28P

Industrial

(-40°C to 85°C)

20 (3)^ 2.7 - 5.

ATmega88P-20AU

ATmega88P-20MU

ATmega88P-20PU

32A

32M1-A

28P

Industrial

(-40°C to 85°C)

Package Type

32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

ATmega48P/88P/168P/328P

7.3 ATmega168P

Note: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 28-1 on page 317 and Figure 28-2 on page 318.

Speed (MHz) (3)^ Power Supply Ordering Code (2)^ Package (1)^ Operational Range

ATmega168PV-10AU

ATmega168PV-10MU

ATmega168PV-10PU

32A

32M1-A

28P

Industrial

(-40°C to 85°C)

ATmega168P-20AU

ATmega168P-20MU

ATmega168P-20PU

32A

32M1-A

28P

Industrial

(-40°C to 85°C)

Package Type

32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28P3 28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32M1-A 32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

ATmega48P/88P/168P/328P

8. Packaging Information

8.1 32A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

R

REV.

32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

32A B

PIN 1 IDENTIFIER

PIN 1

L

C

A1 A2 A

D

D

e E1^ E

B

Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA.

  1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.
  2. Lead coplanarity is 0.10 mm maximum.

A – – 1.

A1 0.05 – 0.

A2 0.95 1.00 1.

D 8.75 9.00 9.

D1 6.90 7.00 7.10 Note 2

E 8.75 9.00 9.

E1 6.90 7.00 7.10 Note 2

B 0.30 – 0.

C 0.09 – 0.

L 0.45 – 0.

e 0.80 TYP

COMMON DIMENSIONS (Unit of Measure = mm)

SYMBOL MIN^ NOM MAX NOTE

ATmega48P/88P/168P/328P

8.2 28M

23 25 Orchard Parkway San Jose, CA 951 31

TITLE DRAWING NO.

R

REV.

28 M1 A

9/7/

28 M1, 2 8 -pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm, 2.4 mm Exposed Pad, Micro Lead Frame Package (MLF)

SIDE VIEW

Pin 1 ID

BOTTOM VIEW

TOP VIEW

Note: The terminal #1 ID is^ a^ Laser-marked Feature.

D

E

e

K

A

C

A

D

E

y

L

b

0.45 (^) COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN^ NOM^ MAX^ NOTE

A 0. 80 0.90 1.

A1 0.00 0.02 0.

b 0.17 0.22 0.

C 0.20 REF

D 3 .95 4.00 4.

D2 2. 35 2.40 2.

E 3 .95 4.00 4.

E2 2. 35 2.40 2.

e 0.

L 0. 35 0.40 0.

y 0.00 – 0.0 8

K 0.20 – –

R 0.