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 2003 Microchip Technology Inc. DS39582B

Data Sheet

28/40/44-Pin Enhanced Flash

Microcontrollers

DS39582B-page ii  2003 Microchip Technology Inc.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.

Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, K EE L OQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Application Maestro, dsPICDEM, dsPICDEM.net, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro®^ 8-bit MCUs, K EE LOQ ®^ code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.

DS39582B-page 2  2003 Microchip Technology Inc.

Pin Diagrams

PIC16F873A/876A

10 11

2 3 4 5 6

1

8

7

9

12 13 14 15

16

17

18

19

20

23

24

25

26

27

28

22 21

MCLR/V PP RA0/AN RA1/AN RA2/AN2/VREF -/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT V SS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI/CCP RC2/CCP RC3/SCK/SCL

RB7/PGD RB6/PGC RB RB RB3/PGM RB RB RB0/INT V DD V SS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA

28-Pin PDIP, SOIC, SSOP

2 3 4 5 6

1

7

MCLR/V

PP

RA2/AN2/VREF-/CVREF RA3/AN3/VREF + RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT VSS OSC1/CLKI 15

16

17

18

19

20

21 RB3/PGM

V DD V SS

RB0/INT

RC7/RX/DT

RC1/T1OSI/CCP

RC2/CCP RC3/SCK/SCLRC4/SDI/SDA

RC5/SDO RC6/TX/CK

28272625242322

RA1/AN1RA0/AN0RB7/PGDRB6/PGCRB5RB

891011121314

28-Pin QFN

PIC16F873A

PIC16F876A

RB RB

RC0/T1OSO/T1CKI

OSC2/CLKO

10 11

2 3 4 5 6

1

12131415 1819202122

38

8

7

444342414039

1617

29

30

31

32

33

23

24

25

26

27

28

363534

9

PIC16F874A

37

RA3/AN3/V

REF

RA2/AN2/V

REF

-/CV

REF

RA0/AN0RA1/AN MCLR/V

PP

RB3/PGMRB6/PGCRB7/PGD

NCRB4RB

RC6/TX/CKRC5/SDORC4/SDI/SDARD3/PSP3RD2/PSP2RD1/PSP1RD0/PSP0RC3/SCK/SCLRC2/CCP1RC1/T1OSI/CCP2RC0/T1OSO/T1CKI

OSC2/CLKO OSC1/CLKI V SS V SS V DD V DD RE2/CS/AN RE1/WR/AN RE0/RD/AN RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT

RC7/RX/DT RD4/PSP RD5/PSP RD6/PSP RD7/PSP V SS V DD V DD RB0/INT RB RB

44-Pin QFN

PIC16F877A

 2003 Microchip Technology Inc. DS39582B-page 3

Pin Diagrams (Continued)

RB7/PGD RB6/PGC RB RB RB3/PGM RB RB RB0/INT V DD V SS RD7/PSP RD6/PSP RD5/PSP RD4/PSP RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP RD2/PSP

MCLR/V PP RA0/AN RA1/AN RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/RD/AN RE1/WR/AN RE2/CS/AN V DD V SS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI/CCP RC2/CCP RC3/SCK/SCL RD0/PSP RD1/PSP

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

PIC16F874A/877A

40-Pin PDIP

10 11 12 13 14 15 16 17 181920212223242526

44 8

7

654321

272829

30

31

32

33

34

35

36

37

38

4342413940

9

PIC16F874A

RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/RD/AN

OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CK NC

RE1/WR/AN RE2/CS/AN V DD V SS

RB3/PGM RB RB RB0/INT V DD V SS RD7/PSP RD6/PSP RD5/PSP RD4/PSP

RA3/AN3/V

REF

RA2/AN2/V

REF

-/CV

REF

RA1/AN1RA0/AN0MCLR/V

PP

NCRB7/PGDRB6/PGCRB5RB4NC

NC

RC6/TX/CK

RC5/SDO RC4/SDI/SDA

RD0/PSP0RD1/PSP1RD2/PSP2RD3/PSP RC3/SCK/SCL

RC2/CCP

RC1/T1OSI/CCP

10 11

2 3 4 5 6

1

12131415 1819202122

38

8

7

444342414039

1617

29

30

31

32

33

23

24

25

26

27

28

363534

9

PIC16F874A

37

RA3/AN3/V

REF

RA2/AN2/V

REF

-/CV

REF

RA0/AN0RA1/AN MCLR/V

NC^ PP

RB6/PGCRB7/PGD

NCRB4RB

RC6/TX/CKRC5/SDORC4/SDI/SDARD3/PSP3RD2/PSP2RD1/PSP1RD0/PSP0RC3/SCK/SCLRC2/CCP1RC1/T1OSI/CCP2NC

NC RC0/T1OSO/T1CKI OSC2/CLKO OSC1/CLKI V SS V DD RE2/CS/AN RE1/WR/AN RE0/RD/AN RA5/AN4/SS/C2OUT RA4/T0CKI/C1OUT

RC7/RX/DT RD4/PSP RD5/PSP RD6/PSP RD7/PSP V SS V DD RB0/INT RB RB RB3/PGM

44-Pin PLCC

44-Pin TQFP

PIC16F877A

PIC16F877A

RC7/RX/DT

 2003 Microchip Technology Inc. DS39582B-page 5

1.0 DEVICE OVERVIEW

This document contains device specific information

about the following devices:

• PIC16F873A
• PIC16F874A
• PIC16F876A
• PIC16F877A

PIC16F873A/876A devices are available only in 28-pin

packages, while PIC16F874A/877A devices are avail-

able in 40-pin and 44-pin packages. All devices in the

PIC16F87XA family share common architecture with

the following differences:

• The PIC16F873A and PIC16F874A have one-half

of the total on-chip memory of the PIC16F876A

and PIC16F877A

• The 28-pin devices have three I/O ports, while the

40/44-pin devices have five

• The 28-pin devices have fourteen interrupts, while

the 40/44-pin devices have fifteen

• The 28-pin devices have five A/D input channels,

while the 40/44-pin devices have eight

• The Parallel Slave Port is implemented only on

the 40/44-pin devices

The available features are summarized in Table 1-1.

Block diagrams of the PIC16F873A/876A and

PIC16F874A/877A devices are provided in Figure 1-

and Figure 1-2, respectively. The pinouts for these

device families are listed in Table 1-2 and Table 1-3.

Additional information may be found in the PICmicro®

Mid-Range Reference Manual (DS33023), which may

be obtained from your local Microchip Sales Represen-

tative or downloaded from the Microchip web site. The

Reference Manual should be considered a complemen-

tary document to this data sheet and is highly recom-

mended reading for a better understanding of the device

architecture and operation of the peripheral modules.

TABLE 1-1: PIC16F87XA DEVICE FEATURES

Key Features PIC16F873A PIC16F874A PIC16F876A PIC16F877A

Operating Frequency DC – 20 MHz DC – 20 MHz DC – 20 MHz DC – 20 MHz

Resets (and Delays) POR, BOR

(PWRT, OST)

POR, BOR

(PWRT, OST)

POR, BOR

(PWRT, OST)

POR, BOR

(PWRT, OST)

Flash Program Memory

(14-bit words)

4K 4K 8K 8K

Data Memory (bytes) 192 192 368 368

EEPROM Data Memory (bytes) 128 128 256 256

Interrupts 14 15 14 15

I/O Ports Ports A, B, C Ports A, B, C, D, E Ports A, B, C Ports A, B, C, D, E

Timers 3 3 3 3

Capture/Compare/PWM modules 2 2 2 2

Serial Communications MSSP, USART MSSP, USART MSSP, USART MSSP, USART

Parallel Communications — PSP — PSP

10-bit Analog-to-Digital Module 5 input channels 8 input channels 5 input channels 8 input channels

Analog Comparators 2 2 2 2

Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions

Packages 28-pin PDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

40-pin PDIP

44-pin PLCC

44-pin TQFP

44-pin QFN

28-pin PDIP

28-pin SOIC

28-pin SSOP

28-pin QFN

40-pin PDIP

44-pin PLCC

44-pin TQFP

44-pin QFN

DS39582B-page 6  2003 Microchip Technology Inc.

FIGURE 1-1: PIC16F873A/876A BLOCK DIAGRAM

Flash

(^13) Data Bus 8

Program 14 Bus

Instruction reg

Program Counter

8 Level Stack (13-bit)

RAM File Registers

Direct Addr 7

RAM Addr (1)^ 9 Addr MUX

Indirect Addr FSR reg

Status reg

MUX

ALU

W reg

Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer

Instruction Decode & Control

Timing Generation OSC1/CLKI OSC2/CLKO

MCLR V DD, V SS

PORTA

PORTB

PORTC

RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT

RB0/INT

RC0/T1OSO/T1CKI RC1/T1OSI/CCP RC2/CCP RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT

8

8

Brown-out Reset

Note 1: Higher order bits are from the Status register.

CCP1,2 Synchronous USART

Timer0 Timer1 Timer2 10-bit A/D

Serial Port

RA3/AN3/VREF +

RA2/AN2/VREF-/CVREF

RA1/AN

RA0/AN

8

3

Data EEPROM

RB RB RB3/PGM RB RB RB6/PGC RB7/PGD

In-Circuit Debugger Low-Voltage Programming

Comparator

Voltage Reference

Device Program Flash Data Memory Data EEPROM PIC16F873A 4K words 192 Bytes 128 Bytes PIC16F876A 8K words 368 Bytes 256 Bytes

Program Memory

DS39582B-page 8  2003 Microchip Technology Inc.

TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION

Pin Name

PDIP, SOIC,

SSOP Pin#

QFN

Pin#

I/O/P

Type

Buffer Type Description

OSC1/CLKI

OSC

CLKI

I

I

ST/CMOS (3)^ Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). OSC2/CLKO OSC

CLKO

O

O

— Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. MCLR/V PP MCLR

VPP

I

P

ST Master Clear (input) or programming voltage (output). Master Clear (Reset) input. This pin is an active low Reset to the device. Programming voltage input. PORTA is a bidirectional I/O port. RA0/AN RA AN

I/O

I

TTL

Digital I/O. Analog input 0. RA1/AN RA AN

I/O

I

TTL

Digital I/O. Analog input 1. RA2/AN2/VREF -/ CVREF RA AN VREF - CVREF

I/O

I

I

O

TTL

Digital I/O. Analog input 2. A/D reference voltage (Low) input. Comparator VREF output.

RA3/AN3/VREF +

RA

AN

VREF +

I/O

I

I

TTL

Digital I/O. Analog input 3. A/D reference voltage (High) input. RA4/T0CKI/C1OUT RA T0CKI C1OUT

I/O

I

O

ST

Digital I/O – Open-drain when configured as output. Timer0 external clock input. Comparator 1 output. RA5/AN4/SS/C2OUT RA AN SS C2OUT

I/O

I

I

O

TTL

Digital I/O. Analog input 4. SPI slave select input. Comparator 2 output. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

 2003 Microchip Technology Inc. DS39582B-page 9

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT RB INT

I/O

I

TTL/ST (1)

Digital I/O. External interrupt. RB1 22 19 I/O^ TTL^ Digital I/O. RB2 23 20 I/O^ TTL^ Digital I/O. RB3/PGM RB PGM

I/O

I

TTL

Digital I/O. Low-voltage (single-supply) ICSP programming enable pin. RB4 25 22 I/O^ TTL^ Digital I/O. RB5 26 23 I/O^ TTL^ Digital I/O. RB6/PGC RB PGC

I/O

I

TTL/ST (2)

Digital I/O. In-circuit debugger and ICSP programming clock. RB7/PGD RB PGD

I/O

I/O

TTL/ST (2)

Digital I/O. In-circuit debugger and ICSP programming data. PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC T1OSO T1CKI

I/O

O

I

ST

Digital I/O. Timer1 oscillator output. Timer1 external clock input. RC1/T1OSI/CCP RC T1OSI CCP

I/O

I

I/O

ST

Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. RC2/CCP RC CCP

I/O

I/O

ST

Digital I/O. Capture1 input, Compare1 output, PWM1 output. RC3/SCK/SCL RC SCK SCL

I/O

I/O

I/O

ST

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I 2 C mode. RC4/SDI/SDA RC SDI SDA

I/O

I

I/O

ST

Digital I/O. SPI data in. I^2 C data I/O. RC5/SDO RC SDO

I/O

O

ST

Digital I/O. SPI data out. RC6/TX/CK RC TX CK

I/O

O

I/O

ST

Digital I/O. USART asynchronous transmit. USART1 synchronous clock. RC7/RX/DT RC RX DT

I/O

I

I/O

ST

Digital I/O. USART asynchronous receive. USART synchronous data. VSS 8, 19 5, 6 P — Ground reference for logic and I/O pins. VDD 20 17 P — Positive supply for logic and I/O pins.

TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED)

Pin Name

PDIP, SOIC,

SSOP Pin#

QFN

Pin#

I/O/P

Type

Buffer Type Description

Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

 2003 Microchip Technology Inc. DS39582B-page 11

PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT RB INT

I/O

I

TTL/ST (1)

Digital I/O. External interrupt. RB1 34 37 9 10 I/O TTL Digital I/O. RB2 35 38 10 11 I/O TTL Digital I/O. RB3/PGM RB PGM

I/O

I

TTL

Digital I/O. Low-voltage ICSP programming enable pin. RB4 37 41 14 14 I/O TTL Digital I/O. RB5 38 42 15 15 I/O TTL Digital I/O. RB6/PGC RB PGC

I/O

I

TTL/ST (2)

Digital I/O. In-circuit debugger and ICSP programming clock. RB7/PGD RB PGD

I/O

I/O

TTL/ST (2)

Digital I/O. In-circuit debugger and ICSP programming data.

TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)

Pin Name

PDIP

Pin#

PLCC

Pin#

TQFP

Pin#

QFN

Pin#

I/O/P

Type

Buffer Type Description

Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

DS39582B-page 12  2003 Microchip Technology Inc.

PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC T1OSO T1CKI

I/O

O

I

ST

Digital I/O. Timer1 oscillator output. Timer1 external clock input. RC1/T1OSI/CCP RC T1OSI CCP

I/O

I

I/O

ST

Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. RC2/CCP RC CCP

I/O

I/O

ST

Digital I/O. Capture1 input, Compare1 output, PWM1 output. RC3/SCK/SCL RC SCK

SCL

I/O

I/O

I/O

ST

Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I^2 C mode. RC4/SDI/SDA RC SDI SDA

I/O

I

I/O

ST

Digital I/O. SPI data in. I 2 C data I/O. RC5/SDO RC SDO

I/O

O

ST

Digital I/O. SPI data out. RC6/TX/CK RC TX CK

I/O

O

I/O

ST

Digital I/O. USART asynchronous transmit. USART1 synchronous clock. RC7/RX/DT RC RX DT

I/O

I

I/O

ST

Digital I/O. USART asynchronous receive. USART synchronous data.

TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED)

Pin Name

PDIP

Pin#

PLCC

Pin#

TQFP

Pin#

QFN

Pin#

I/O/P

Type

Buffer Type Description

Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

DS39582B-page 14  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS39582B-page 15

2.0 MEMORY ORGANIZATION

There are three memory blocks in each of the

PIC16F87XA devices. The program memory and data

memory have separate buses so that concurrent

access can occur and is detailed in this section. The

EEPROM data memory block is detailed in Section 3.

“Data EEPROM and Flash Program Memory”.

Additional information on device memory may be found

in the PICmicro ®^ Mid-Range MCU Family Reference

Manual (DS33023).

FIGURE 2-1: PIC16F876A/877A

PROGRAM MEMORY MAP AND STACK

2.1 Program Memory Organization

The PIC16F87XA devices have a 13-bit program

counter capable of addressing an 8K word x 14 bit

program memory space. The PIC16F876A/877A

devices have 8K words x 14 bits of Flash program

memory, while PIC16F873A/874A devices have

4K words x 14 bits. Accessing a location above the

physically implemented address will cause a

wraparound.

The Reset vector is at 0000h and the interrupt vector is

at 0004h.

FIGURE 2-2: PIC16F873A/874A PROGRAM MEMORY MAP AND STACK

PC<12:0>

13

0000h

0004h 0005h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-Chip

CALL, RETURN

RETFIE, RETLW

1FFFh

Stack Level 2

Program Memory

Page 0

Page 1

Page 2

Page 3

07FFh 0800h

0FFFh 1000h

17FFh 1800h

PC<12:0>

13

0000h

0004h 0005h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-Chip

CALL, RETURN

RETFIE, RETLW

1FFFh

Stack Level 2

Program Memory

Page 0

Page 1

07FFh 0800h

0FFFh 1000h

 2003 Microchip Technology Inc. DS39582B-page 17

FIGURE 2-3: PIC16F876A/877A REGISTER FILE MAP

Indirect addr. (*)

TMR

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PCLATH

INTCON

PIR

TMR1L

TMR1H

T1CON

TMR

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

OPTION_REG

PCL

STATUS

FSR

TRISA

TRISB

TRISC

PCLATH

INTCON

PIE

PCON

PR

SSPADD

SSPSTAT

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

7Fh FFh

Bank 0 Bank 1

Unimplemented data memory locations, read as ‘ 0 ’.

* Not a physical register.

Note 1: These registers are not implemented on the PIC16F876A.

2: These registers are reserved; maintain these registers clear.

File

Address

Indirect addr. ()^ Indirect addr. ()

PCL

STATUS

FSR

PCLATH

INTCON

PCL

STATUS

FSR

PCLATH

INTCON

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

11Fh

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

19Fh

120h 1A0h

17Fh 1FFh

Bank 2 Bank 3

Indirect addr. (*)

PORTD (1)

PORTE (1)

TRISD (1)

ADRESL

TRISE (1)

TMR0 OPTION_REG

PIR2 PIE

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRESH

ADCON

TXSTA

SPBRG

ADCON

General

Purpose

Register

General

Purpose

Register

General

Purpose

Register

General

Purpose

Register

1EFh

accesses 1F0h

70h - 7Fh

EFh

accesses F0h

70h-7Fh

16Fh

accesses 170h

70h-7Fh

General

Purpose

Register

General

Purpose

Register

PORTB TRISB

96 Bytes

80 Bytes 80 Bytes 80 Bytes

16 Bytes 16 Bytes

SSPCON

EEDATA

EEADR

EECON

EECON

EEDATH

EEADRH

Reserved (2)

Reserved (2)

File

Address

File

Address

File

Address

CMCON

CVRCON

DS39582B-page 18  2003 Microchip Technology Inc.

FIGURE 2-4: PIC16F873A/874A REGISTER FILE MAP

Indirect addr. (*)

TMR

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PCLATH

INTCON

PIR

TMR1L

TMR1H

T1CON

TMR

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

OPTION_REG

PCL

STATUS

FSR

TRISA

TRISB

TRISC

PCLATH

INTCON

PIE

PCON

PR

SSPADD

SSPSTAT

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

7Fh FFh

Bank 0 Bank 1

Indirect addr. ()^ Indirect addr. ()

PCL

STATUS

FSR

PCLATH

INTCON

PCL

STATUS

FSR

PCLATH

INTCON

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

17Fh 1FFh

Bank 2 Bank 3

Indirect addr. (*)

PORTD (1)

PORTE (1)

TRISD (1)

ADRESL

TRISE (1)

TMR0 OPTION_REG

PIR2 PIE

RCSTA

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRESH

ADCON

TXSTA

SPBRG

ADCON

General

Purpose

Register

General

Purpose

Register

1EFh

1F0h

accesses

A0h - FFh

16Fh

170h

accesses

20h-7Fh

PORTB TRISB

96 Bytes 96 Bytes

SSPCON

10Ch

10Dh

10Eh

10Fh

110h

18Ch

18Dh

18Eh

18Fh

190h

EEDATA

EEADR

EECON

EECON

EEDATH

EEADRH

Reserved (2)

Reserved (2)

Unimplemented data memory locations, read as ‘ 0 ’.

* Not a physical register.

Note 1: These registers are not implemented on the PIC16F873A.

2: These registers are reserved; maintain these registers clear.

120h 1A0h

File

Address

File

Address

File

Address

File

Address

CMCON

CVRCON