Baixe Conversores AD&DA e outras Notas de estudo em PDF para Eletrônica, somente na Docsity!
CHAPTER
Digital-to-Analog and
Analog-to-Digital Conversions
OUTLINE
13.1 Resistor Networks for Digital-to-Analog Conversion
13.2 The TTL Digital-to-Analog Converter
13.3 Analog-to-Digital Conversion Using Voltage Comparators
13.4 The Count-Up and Compare Analog-to-Digital Converter
13.5 The Successive Approximation Analog-to-Digital Converter
13.6 The DAC0830 Digital-to-Analog Converter Integrated Circuit
13.7 Making the Logic for a 3-Bit Voltage Comparator Analog-to-Digital Converter
13.8 Troubleshooting Digital-to-Analog Converters
Digital Application Analog-to-Digital Converters
LAB 13A Digital-to-Analog and Analog-to-Digital
LAB 13B Analog-to-Digital Converters
KEY TERMS
analog-to-digital
binary ladder
digital-to-analog
flash converter successive approximation 2 R ladder
OBJECTIVES
After completing this chapter, you should be able to:
- Use resistor networks for digital-to-analog conversion.
- Explain the operation of a TTL digital-to-analog converter.
- Use voltage comparators to produce an analog-to-digital converter.
- Describe the count-up and compare method of analog-to-digital conversion.
- Describe the successive approximation method of analog-to-digital conversion.
15 V output voltage. If all the switches are switched to the 0 position, the output is 0 V or ground, as shown in Figure 13-3. Now let us analyze the switch configuration in Figure 13-1. The equivalent cir- cuit is shown in Figure 13-4. If we reduce the circuit to two series-equivalent resistors, the voltage output will be the voltage drop across R (^) B. Using the voltage divider for- mula, we can find the output voltage for the binary number 1000 or decimal number 8 to be 8 V.
RB =
k k k
k
Ω Ω Ω
V V
R
S R R
B A B
OUT =^ +
V OUT V
k k k
V OUT = 8 V
The output voltage for the other possible binary number inputs can be computed in a similar manner. You will find the voltage increments to be 1 V for this binary ladder. The binary number equivalent to 10 produces a voltage of 10 volts and the binary number equivalent to 7 produces a voltage of 7 volts. In other words, the supply voltage is in increments equal to the supply voltage divided by the largest binary num- ber which can be input to the resistor network. Therefore, the voltage increment for a binary ladder is found by using the following formula.
488 CHAPTER 13
FIGURE 13-3 Binary ladder with all zeros on the input
FIGURE 13-4 Equivalent circuit for the binary ladder with 1000 on the input
Binary ladder voltage increment = −
V S
2 N 1
where voltage supply number of bits in the binar
V S =
N = y number input
When N equals the number of bits in the binary number input to the binary ladder, (^2) N − 1 is the largest number that can be expressed for a binary number of N bits. If this formula is the amount of each increment, the final output voltage must be equal to the binary number input times the binary ladder voltage increment. The following formula is used for the voltage output of the circuit shown in Figure 13-1.
Binary ladder: V OUT binary number input
V S
= N −
The values of the resistors in the binary ladder are divided by 2 for each binary power increase, that is, a 2 0 resistor is 8 kΩ, a 2 1 resistor is 4 kΩ, a 2 2 resistor is 2 kΩ, and a 2 3 resistor is 1 kΩ. If a fifth bit is added to the binary ladder, the resistor value is one-half the 2 3 resistor or 500 Ω. You can see that the larger the binary number, the smaller the resistor. It is not easy to get resistors with the exact values that fit this pattern. These two problems can be eliminated by using another type of resistor network to pro- duce the proportional output voltage. This is the 2 R network shown in Figure 13-5. Using the same method shown in Fig- ure 13-4, we can determine the output voltage for the binary number switched into the 2 R network in Figure 13-5. This is shown in Figure 13-6. The 2 R ladder is similar to the binary ladder except that the voltage increments are equal to the voltage supply divided by the total number of combi- nations in the binary number
DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERSIONS 489
FIGURE 13-5 2 R D-to-A converter
∆ V =
∆ V = 0 1. volts
Next, use the voltage increment ∆ V to obtain the output voltage.
V
V S
OUT =^ Binary Number^ × 2 8
V OUT = 78 ×0 1.
V OUT = 7 8. volts
EXAMPLE 13- What would be the voltage increment ∆ V of a 5-bit binary ladder with a voltage supply of 15.5 volts?
Solution
∆ V
V S
= 2 N − 1
∆ V =
. V
∆ V = 15 5
. V
∆ V = .5 volts
Yv
13.2 THE TTL DIGITAL-TO-ANALOG CONVERTER The binary number in the two previous networks was not a TTL level input. To make the network work, the 1 voltage must be the supply voltage, and the 0 voltage must be ground or 0 volts. The TTL output voltage will give a good 0 voltage, or in the worst case, 0.4 volts, but the 1 voltage is typically about 3.5 volts. By using an open-collector output, such as the 7406 inverter or 7407 has, and a pull-up resistor to V (^) S , we can con- vert the TTL level voltages to the voltage needed by the D-to-A network. The output voltage of the 7406 is not absolute ground or absolute V (^) S , but it is very close. This is shown in Figure 13-7.
DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERSIONS 491
Figure 13-8 shows this type of buffer used to make a TTL D-to-A converter where the top output voltage is 15 volts. When the output of the 7406 goes LOW, it will go to 0.1 V or 0.2 volts above ground at best, which introduces some error into the D-to-A converter; and when the 7406 output goes to HiZ, the 1-kΩ resistor pulls the 20-kΩ resistor up to +16 V. In doing so, it adds its 1-kΩ resistor to the 20-kΩ resistor. This means the 2 R resistor is a little larger (5 percent in this case) when it is at +16 V and does not quite reach ground when it is brought LOW.
These errors can be eliminated by other methods; but for many uses of D-to-A converters, these errors are tolerable. Figure 13-9 shows a D-to-A converter used to control the speed of a small dc motor such as might be used on a robotic arm. Notice the operational amplifier used to buffer the D-to-A converter.
492 CHAPTER 13
FIGURE 13-7 Converting TTL voltage levels to D-to-A levels
FIGURE 13-8 A TTL 2 R D-to-A converter
Yv
13.3 ANALOG-TO-DIGITAL CONVERSION USING VOLTAGE COMPARATORS The voltage comparator, which was discussed in the chapter on clocks, can be used to make a very fast analog-to-digital converter. An analog-to-digital converter produces a binary number which is in direct proportion to an analog voltage input. Figure 13-10 shows a 3-bit A-to-D converter made from seven LM339 voltage comparators. The negative input of each comparator is tied to a resistor voltage divider which divides the 8-volt supply into 1-volt increments. Each voltage comparator has a reference voltage of 1 volt greater than the previous comparator. All of the positive inputs to the comparators are tied together so the input voltage will increase on all comparators at the same time. If the input voltage increases to 2.5 volt, the output of the first two comparators will be +5 V or logic 1 because the positive input will be greater than the negative in- put; but the rest of the comparators’ outputs will be at ground or logic 0. The output of the LM339 is an open-collector output; so by using a pull-up resistor to +5 V, the out- put will be standard TTL levels even though the input may increase to 8 volts. As the voltage increases to 3.5 volts, the third comparator’s output will change to a logic 1. If the analog voltage increases to above 7 volts, all the comparators will be at logic 1. The comparators will go to logic 0 when the input voltage goes below the reference voltages set by the voltage divider. The output of all the comparators is decoded to form a 3-bit binary number by the logic gates shown in Figure 13-10. When all the comparators’ outputs are at logic 0, the outputs of their corresponding NAND gates are 1, because any 0 into a NAND gate produces a 1 output. If the analog input voltage rises to 1.5 volts, the first comparator’s output goes to logic 1 which is fed to the two-input NAND gate. The other input to this NAND gate is from the inverter which comes off the output of the second comparator. The output of the second comparator is still 0 because the analog voltage is still 1. volts and is not yet large enough to change the state of the second comparator. This 0 is inverted to a 1 and fed to the input of the NAND gate for the first comparator. At this point, the first NAND gate has 1 and 1 on its inputs and 0 on its output, which is fed to the 2 0 NAND gate. This produces a logic 1 or binary number 1 on the output of the 2 0 NAND gate. A binary number 1 on the output means that the analog input voltage lies between 1 and 2 volts. When the input voltage increases to 2.5 volts, the second comparator’s output will also be logic 1. This produces a 0 on the inverter’s output which inhibits the first NAND gate, thus removing the 1 on the 2 0 NAND gate’s output. The logic 1 on the second comparator’s output enables the second NAND gate, producing a 0 on its out- put which produces a logic 1 or binary number 10 on the output of the 2 1 NAND gate. This means that the analog input lies between 2 and 3 volts. It can be seen that as the voltage increases, the binary output of the A-to-D converter will change to reflect the value of the analog input.
494 CHAPTER 13
In order to increase the accuracy of the comparator in Figure 13-10, you need more comparators and NAND gates. This is a major drawback for this type of A-to-D con- verter; but it operates very fast. The only thing to slow it down is the propagation delay of the comparator and NAND gates, which is on the order of 50 ns to 75 ns. Because of its speed, this type of A-to-D converter is often called a flash converter.
DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERSIONS 495
VIN
8 V
1 kΩ
1 kΩ
1 kΩ
1 kΩ
1 kΩ
1 kΩ
1 kΩ
1 kΩ
1 kΩ
1 kΩ
1 kΩ
1 kΩ
1 kΩ
1 kΩ
1 kΩ
7
6
5
7
4
3
2
1 1
2
3
4
5
6
LM
22
21
20
FIGURE 13-10 An A-to-D converter using voltage comparators
fed from the comparator enables the NAND gate, and the clock is passed on to the 7493 counter. As the counter counts, its display gets larger and the analog voltage output of the 2 R resistor network also gets larger. When the voltage at the negative input of the voltage comparator gets larger than the analog voltage input to the positive input of the comparator, the output of the comparator goes LOW. This inhibits the NAND gate and stops the clock and the 7493 counter. The stopped counter will now contain the binary number which pro- duces a voltage one increment of the D-to-A converter larger than the analog input voltage. The A-to-D converter stays at this point until the RESET button is pushed or until the analog input voltage increases, at which time the counter simply counts back up to the new voltage. If the analog input voltage drops after the counter stops, the counter does not change and has to be reset to count back up to the lower voltage. Figure 13- shows the waveform for the analog output of the D-to-A converter as the analog input voltage changes.
To increase the accuracy of the count-up and compare A-to-D converter, increase the size of the counter and the D-to-A converter. In the case of the A-to-D converter in Figure 13-11, if you added one more 7493 to the converter, the +16 V would be divided into 256 increments as compared to 16 increments with one 7493 counter. The main drawback to this type of A-to-D converter is speed because of the time it takes to count-up and compare.
EXAMPLE 13- Draw the logic schematic for an analog-to-digital converter like the one in Fig- ure 13-11 that has 8-bit resolution.
Solution Refer to Figure 13-13.
DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERSIONS 497
FIGURE 13-12 D-to-A converter waveforms
Yv
13.5 THE SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER This type of A-to-D converter also uses a D-to-A converter and a voltage comparator, but it uses a different technique to determine the binary number to feed into the D-to-A converter.
498 CHAPTER 13
A B
Q (^) A Q (^) B Q (^) C U1 Q (^) D R0(1) R0(2)
14 1
2 3
12 9 8 11
74LS
1
3
5
9
11
13
1
3
2
4
6
8
10
12
2
4
4 5 3
2
2 1
3
(^12) 16 V
A B
Q (^) A Q (^) B Q (^) C U2 Q (^) D R0(1) R0(2)
14 1
2 3
12 9 8 11
74LS
7407
7407
7407
7407
7407
7407
7407
7407
U4B
U4A
U3F
U3E
U3D
U3C
U3B
U3A
74LS
LM
U5A
U6A
1 k RESET
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
1 k
1 k
1 k
1 k
1 k
1 k
1 k
1 k
20 k
20 k
20 k
20 k
20 k
20 k
20 k
20 k 20 k
10 k
10 k
10 k
10 k
10 k
10 k
10 k
V (^) CC CLOCK
Input Voltage
V (^) CC
1 k
16 V
FIGURE 13-
The successive approximation method just described takes only four cycles to de- termine the correct binary number for the given analog input voltage, and it takes the same time to determine a large number as a small one. Therefore, the successive ap- proximation method is faster than the count-up method but not as fast as the voltage comparator method. Figure 13-15 shows a successive approximation A-to-D converter which uses a CP and CP ′ nonoverlapping clock generator, shift register and storage registers. When the RESET button is pushed, the clock generator and A flip-flop are preset to 1 while all the rest of the flip-flops are reset to 0. The A-to-D converter will stay in this configura- tion until the RESET button is released, thus allowing the clock generator flip-flop to run. After the clock is allowed to run, Q (^) A is preset to 1 which places a 1 on the 2 3 or most significant bit of the D-to-A converter. The contents of the comparator are fed to
500 CHAPTER 13
J K
Q Q
PR
CL
CP
C P '
Clock
+5 V
+5 V +5 V
+5 V
+5 V
+5 V
+5 V
VCC
J K
Q Q
PR
CL^ –
J K
Q Q
PR
CL^ –
+5 V
J K
Q Q
PR
CL^ –
+5 V
J K
Q Q
PR
CL^ –
+5 V
J K
Q Q
PR
CL^ –
+5 V
+5 V
J K
Q Q
PR
CL^ –
+5 V
+5 V
J K
Q Q
PR
CL^ –
+5 V
+5 V
J K
Q Q
PR
CL^ –
2 3 2 2
7406 1
2 1 2 0
+16 V 1 kΩ 1 kΩ 1 kΩ
10 kΩ 10 kΩ 10 kΩ
20 kΩ 20 kΩ 20 kΩ
Analog Input
RESET
20 kΩ
20 kΩ
A B C D
AS BS CS DS
LM
12.5 V
1 kΩ
FIGURE 13-15 A successive approximation A-to-D converter
an AND gate which is controlled by the CP clock of the nonoverlapping clock genera- tor. When it goes HIGH, the content of the comparator is passed through the AND gate to the A (^) S storage flip-flop NAND gate. If the comparator is 1, the flip-flop will be set; if it is 0, the flip-flop will not be set. Next comes the CP ′ clock which shifts the A , B , C , and D flip-flop shift register 1 place. This makes Q (^) B a 1 and the cycle is repeated. After the 1, which was generated in Q (^) A by the RESET pulse, is shifted out of the A , B , C , and D flip-flop shift register, the correct binary number is present on the 2 0 and 2 3 outputs. Notice that it took only four CP ′ pulses to obtain the correct binary number. Figure 13-16 shows the waveforms for the operation of the A-to-D converter in Fig- ure 13-15.
3 SELF-CHECK 2 1. Which analog-to-digital conversion method will be the fastest for all values of volt- ages to be converted?
- Draw the waveforms for the D-to-A output in Figure 13-16 as if the analog input voltage of the successive approximation counter were 7.5 volts.
- Design a count-up and compare A-to-D converter like the one shown in Fig- ure 13-11. Use one 7407, one 74LS93, one 74LS08, and one LM339 IC. Show pin numbers.
DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERSIONS 501
FIGURE 13-16 Waveforms for the successive approximation A-to-D converter in Figure 13-
FIGURE 13-17A
D^7
Q
7
D^6
Q
6
D^5
Q
5
D^4
Q
4
D^3
Q
3
D^2
Q
2
D^1
Q
1
D^0
Q
0
D^7
Q
7
D^6
Q
6
D^5
Q
5
D^4
Q
4
D^3
Q
3
D^2
Q
2
D^1
Q
1
D^0
Q
0
DA T A B U S ILE CS
WR
1 WR
2 XERF
13 14 15 16 4 5 6 7 19 1 2 18 17
DAC
(^10000000)
2 R 2 R 2 R 2 R 2 R 2 R 2 R 2 R
2 R
2 R
R R R R R R R
Rfb
+12 V^ – 12 V
8
-^ 2.5VoltsOut
3
4
(^91112)
GNDGNDV^ CC
V^ REF
7 1 5
7416
3 10 20
+5 V^2
+12 V +^ –
FIGURE 13-17B
