Datasheet do circuito integrado 74LS193 | Manuais, Projetos, Pesquisas Eletrônica Digital

September 1986

Revised March 2000

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

DM74LS193

Synchronous 4-Bit Binary Counter with Dual Clock

General Description

The DM74LS193 circuit is a synchronous up/down 4-bit

binary counter. Synchronous operation is provided by hav-

ing all flip-flops clocked simultaneously, so that the outputs

change together when so instructed by the steering logic.

This mode of operation eliminates the output counting

spikes normally associated with asynchronous (ripple-

clock) counters.

The outputs of the four ma ster-slave flip-flops are triggered

by a LOW-to-HIGH level transition of either count (clock)

input. The direction of counting is determined by which

count input is pulsed while the other count input is held

HIGH.

The counter is fully p rogrammable; that is, each output may

be preset to either level by entering the desired data at the

inputs while the load input is LOW. The output will change

independently of the count pulses. This feature allows the

counters to be used as modulo-N dividers by simply modi-

fying the count length with the p reset inputs.

A clear input has been provided which, when taken to a

high level, forces all outputs to the low level; independent

of the count and load inputs. The clear, count, and load

inputs are buffered to lower the drive requirements of clock

drivers, etc., required for long words.

These counters were design ed to be cascaded without the

need for external circuitry. Both borrow and carry outputs

are available to cascade both the up and down counting

functions. The borrow output produces a pulse equal in

width to the count down input when the counter un derflows.

Similarly, the carry output produces a pulse equal in width

to the count down inpu t when an overflow condition exists.

The counters can then be easily cascaded by feeding the

borrow and carry outputs to the count down and count up

inputs respectively of the succeeding counter.

Features

■Fully independent clear inp ut

■Synchronous operation

■Cascading circuitry provided in ternally

■Individual preset each flip-flop

Ordering Code:

Connection Diagram

Order Number Package Number Package Description

DM74LS193M M16A 16-Lead Small Outline Integ rated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

DM74LS193N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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Baixe Datasheet do circuito integrado 74LS193 e outras Manuais, Projetos, Pesquisas em PDF para Eletrônica Digital, somente na Docsity!

© 2000 Fairchild Semiconductor Corporation DS006406 www.fairchildsemi.com

September 1986

Revised March 2000

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

DM74LS

Synchronous 4-Bit Binary Counter with Dual Clock

General Description

The DM74LS193 circuit is a synchronous up/down 4-bit

binary counter. Synchronous operation is provided by hav-

ing all flip-flops clocked simultaneously, so that the outputs

change together when so instructed by the steering logic.

This mode of operation eliminates the output counting

spikes normally associated with asynchronous (ripple-

clock) counters.

The outputs of the four master-slave flip-flops are triggered

by a LOW-to-HIGH level transition of either count (clock)

input. The direction of counting is determined by which

count input is pulsed while the other count input is held

HIGH.

The counter is fully programmable; that is, each output may

be preset to either level by entering the desired data at the

inputs while the load input is LOW. The output will change

independently of the count pulses. This feature allows the

counters to be used as modulo-N dividers by simply modi-

fying the count length with the preset inputs.

A clear input has been provided which, when taken to a

high level, forces all outputs to the low level; independent

of the count and load inputs. The clear, count, and load

inputs are buffered to lower the drive requirements of clock

drivers, etc., required for long words.

These counters were designed to be cascaded without the

need for external circuitry. Both borrow and carry outputs

are available to cascade both the up and down counting

functions. The borrow output produces a pulse equal in

width to the count down input when the counter underflows.

Similarly, the carry output produces a pulse equal in width

to the count down input when an overflow condition exists.

The counters can then be easily cascaded by feeding the

borrow and carry outputs to the count down and count up

inputs respectively of the succeeding counter.

Features

n Fully independent clear input

n Synchronous operation

n Cascading circuitry provided internally

n Individual preset each flip-flop

Ordering Code:

Connection Diagram

Order Number Package Number Package Description

DM74LS193M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

DM74LS193N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

DM74LS

Logic Diagram

DM74LS

Absolute Maximum Ratings (Note 1) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Recommended Operating Conditions

Note 2: CL = 15 pF, RL = 2 kΩ, IA = 25 °C and VCC = 5V. Note 3: CL = 50 pF, RL = 2 kΩ, IA = 25 °C and VCC = 5V. Note 4: TA = 25 °C and VCC = 5V.

DC Electrical Characteristics

Note 5: All typicals are at VCC = 5V, TA = 25 °C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: ICC is measured with all outputs open, CLEAR and LOAD inputs grounded, and all other inputs at 4.5V.

Operating Free Air Temperature Range − 0 °C to + 70 °C

Supply Voltage 7V

Input Voltage 7V

Storage Temperature Range − 65 °C to + 125 °C

Symbol Parameter Min Nom Max Units

V CC Supply Voltage 4.75 5 5.25 V

V IH HIGH Level Input Voltage 2 V

V IL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

fCLK Clock Frequency (Note 2) 0 25

MHz

Clock Frequency (Note 3)

tW Pulse Width of any Input (Note 4) 20 ns

tSU Data Setup Time (Note 4) 20 ns

tH Data Hold Time (Note 4) 0 ns

tEN Enable Time to Clock (Note 4) 40 ns

TA Free Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units (Note 5) VI Input Clamp Voltage V (^) CC = Min, I (^) I = −18 mA −1.5 V VOH HIGH Level Output V (^) CC = Min, I (^) OH = Max 2.5 3. V Voltage V (^) IL = Max, VIH = Min 2.7 3. VOL LOW Level Output V (^) CC = Min, I (^) OL = Max 0.25 0. Voltage V (^) IL = Max, VIH = Min 0.35 0.5 V I (^) OL = 4 mA, V (^) CC = Min 0.25 0. I (^) I Input Current @ Max Input Voltage V (^) CC = Max, VI = 7V 0.1 mA I (^) IH HIGH Level Input Current V (^) CC = Max, VI = 2.7V 20 μA I (^) IL LOW Level Input Current V (^) CC = Max, VI = 0.4V −0.4 mA I (^) OS Short Circuit V (^) CC = Max − 20 − 100 mA Output Current (Note 6) − 20 − 100 I (^) CC Supply Current V (^) CC = Max (Note 7) 19 34 mA

DM74LS AC Electrical Characteristics

From (Input) RL = 2 k Ω Symbol Parameter To (Output) CL = 15 pF C (^) L = 50 pF Units Min Max Min Max f (^) MAX Maximum Clock Frequency 25 20 MHz t (^) PLH Propagation Delay Time Count Up 26 30 ns LOW-to-HIGH Level Output to Carry t (^) PHL Propagation Delay Time Count Up 24 36 ns HIGH-to-LOW Level Output to Carry t (^) PLH Propagation Delay Time Count Down 24 29 ns LOW-to-HIGH Level Output to Borrow t (^) PHL Propagation Delay Time Count Down 24 32 ns HIGH-to-LOW Level Output to Borrow t (^) PLH Propagation Delay Time Either Count 38 45 ns LOW-to-HIGH Level Output to Any Q t (^) PHL Propagation Delay Time Either Count 47 54 ns HIGH-to-LOW Level Output to Any Q t (^) PLH Propagation Delay Time Load to 40 41 ns LOW-to-HIGH Level Output Any Q t (^) PHL Propagation Delay Time Load to 40 47 ns HIGH-to-LOW Level Output Any Q t (^) PHL Propagation Delay Time Clear to 35 44 ns HIGH-to-LOW Level Output Any Q

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Datasheet do circuito integrado 74LS193, Manuais, Projetos, Pesquisas de Eletrônica Digital

Documentos relacionados

Pré-visualização parcial do texto

Baixe Datasheet do circuito integrado 74LS193 e outras Manuais, Projetos, Pesquisas em PDF para Eletrônica Digital, somente na Docsity!

© 2000 Fairchild Semiconductor Corporation DS006406 www.fairchildsemi.com

September 1986

Revised March 2000

DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock

DM74LS

Synchronous 4-Bit Binary Counter with Dual Clock

General Description

The DM74LS193 circuit is a synchronous up/down 4-bit

binary counter. Synchronous operation is provided by hav-

ing all flip-flops clocked simultaneously, so that the outputs

change together when so instructed by the steering logic.

This mode of operation eliminates the output counting

spikes normally associated with asynchronous (ripple-

clock) counters.

The outputs of the four master-slave flip-flops are triggered

by a LOW-to-HIGH level transition of either count (clock)

input. The direction of counting is determined by which

count input is pulsed while the other count input is held

HIGH.

The counter is fully programmable; that is, each output may

be preset to either level by entering the desired data at the

inputs while the load input is LOW. The output will change

independently of the count pulses. This feature allows the

counters to be used as modulo-N dividers by simply modi-

fying the count length with the preset inputs.

A clear input has been provided which, when taken to a

high level, forces all outputs to the low level; independent

of the count and load inputs. The clear, count, and load

inputs are buffered to lower the drive requirements of clock

drivers, etc., required for long words.

These counters were designed to be cascaded without the

need for external circuitry. Both borrow and carry outputs

are available to cascade both the up and down counting

functions. The borrow output produces a pulse equal in

width to the count down input when the counter underflows.

Similarly, the carry output produces a pulse equal in width

to the count down input when an overflow condition exists.

The counters can then be easily cascaded by feeding the

borrow and carry outputs to the count down and count up

inputs respectively of the succeeding counter.

Features

n Fully independent clear input

n Synchronous operation

n Cascading circuitry provided internally

n Individual preset each flip-flop

Ordering Code:

Connection Diagram

Order Number Package Number Package Description

DM74LS193M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body

DM74LS193N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Operating Free Air Temperature Range − 0 °C to + 70 °C

Supply Voltage 7V

Input Voltage 7V

Storage Temperature Range − 65 °C to + 125 °C

Symbol Parameter Min Nom Max Units

V CC Supply Voltage 4.75 5 5.25 V

V IH HIGH Level Input Voltage 2 V

V IL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −0.4 mA

IOL LOW Level Output Current 8 mA

fCLK Clock Frequency (Note 2) 0 25

MHz

Clock Frequency (Note 3)

tW Pulse Width of any Input (Note 4) 20 ns

tSU Data Setup Time (Note 4) 20 ns

tH Data Hold Time (Note 4) 0 ns

tEN Enable Time to Clock (Note 4) 40 ns

TA Free Air Operating Temperature 0 70 °C

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein: