Baixe MCP4716A0T Datasheet e outras Trabalhos em PDF para Eletrônica Digital, somente na Docsity!
© 2011-2012 Microchip Technology Inc. DS22272C-page 1
Features:
- Output Voltage Resolutions:
- 12-bit: MCP
- 10-bit: MCP
- 8-bit: MCP
- Rail-to-Rail Output
- Fast Settling Time of 6 μs (typical)
- DAC Voltage Reference Options:
- Output Gain Options:
- Unity (1x)
- 2x, only when V (^) REF pin is used as voltage source
- Nonvolatile Memory (EEPROM):
- Auto Recall of Saved DAC register setting
- Auto Recall of Saved Device Configuration (Voltage Reference, Gain, Power-Down)
- Power-Down modes:
- Disconnects output buffer
- Selection of V (^) OUT pull-down resistors (640 kΩ, 125 kΩ, or 1 kΩ)
- Low-Power Consumption:
- Normal Operation: 210 μA typical
- Power-Down Operation: 60 nA typical (PD1:PD0 = 11 )
- Single-Supply Operation: 2.7V to 5.5V
- I 2 C™ Interface:
- Eight Available Addresses
- Standard (100 kbps), Fast (400 kbps), and High-Speed (3.4 Mbps) modes
- Small 6-lead SOT-23 and DFN (2x2) Packages
- Extended Temperature Range: -40°C to +125°C
Applications:
- Set Point or Offset Trimming
- Sensor Calibration
- Low-Power Portable Instrumentation
- PC Peripherals
- Data Acquisition Systems
- Motor Control
Package Types
Description:
The MCP4706/4716/4726 are single channel 8-bit, 10-bit, and 12-bit buffered voltage output Digital-to- Analog Converters (DAC) with nonvolatile memory and an I 2 C serial interface. This family will also be referred to as MCP47X6. The VREF pin or the device VDD can be selected as the DAC’s reference voltage. When V (^) DD is selected, V (^) DD is connected internally to the DAC reference circuit. When the VREF pin is used, the user can select the output buffer’s gain to 1 or 2. When the gain is 2, the VREF pin voltage should be limited to a maximum of VDD/2. The DAC register value and Configuration bits can be programmed to nonvolatile memory (EEPROM). The nonvolatile memory holds the DAC register and Configuration bit values when the device is powered off. A device Reset (such as a Power-on Reset) latches these stored values into the volatile memory. Power-Down modes enable system current reduction when the DAC output voltage is not required. The V (^) OUT pin can be configured to present a low, medium, or high resistance load. These devices have a two-wire I 2 C™ compatible serial interface for standard (100 kHz), fast (400 kHz), or High-Speed (3.4 MHz) mode. These devices are available in small 6-pin SOT-23 and DFN 2x2 mm packages.
1
2
3 4
5
VOUT 6
SCL
SDA
VSS
SOT-23-
VDD
MCP4706/16/
2x2 DFN-6*
SCL
SDA
VSS
VOUT EP 7 VDD
- Includes Exposed Thermal Pad (EP); see Table 3-1.
V VREF REF
8-/10-/12-Bit Voltage Output Digital-to-Analog Converter
with EEPROM and I
2 C™ Interface
DS22272C-page 2 © 2011-2012 Microchip Technology Inc.
Block Diagram
VDD
VSS
SCL
SDA
VOUT
DAC
Register
EEPROM
PD1:PD
Op Amp
2 I
C™ Interface Logic
VRL
1 k
125 k
640 k
VDD
Buffer
Gain (1x or 2x) (G = 0 or 1 )
Resistor Ladder
Reference
VREF1 :VREF
Selection
Control Logic
VREF
VW
PD1:PD
DS22272C-page 4 © 2011-2012 Microchip Technology Inc.
ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, V (^) DD = 2.7V to 5.5V, V (^) SS = 0V, R L = 5 kΩ from V (^) OUT to GND, CL = 100 pF, TA = -40°C to +125°C. Typical values at +25°C. Parameters Symbol Min Typical Max Units Conditions Power Requirements Input Voltage V (^) DD 2.7 — 5.5 V Input Current I (^) DD — 210 400 μA V (^) REF1:VREF0 = 00 , SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 0 x 000 — 210 400 μA V (^) REF1:VREF0 = 11 , VREF = V (^) DD, SCL = SDA = VSS, VOUT is unloaded, volatile DAC Register = 0 x 000 Power-Down Current I (^) DDP — 0.09 2 μA PD1:PD0 = 01 ( Note 6 ), VOUT not connected Power-On Reset Threshold
VPOR — 2.2 — V RAM retention voltage, (VRAM ) < VPOR
Power-Up Ramp Rate VRAMP 1 — — V/S (Note 1, Note 4) DC Accuracy Offset Error VOS ±0.02 0.75 % of FSR Code = 0x000h VREF1:VREF0 = 00 , G = 0 Offset Error Temperature Coefficient
VOS/°C — ±1 — ppm/°C -40°C to +25°C — ±2 — ppm/°C +25°C to +85°C Zero-Scale Error EZS — 0.13 2.0 LSb MCP4706 , Code = 0x00h — 0.52 7.7 LSb MCP4716 , Code = 0x000h — 2.05 30.8 LSb MCP4726 , Code = 0x000h Full-Scale Error EFS — 0.3 5.2 LSb MCP4706 , Code = 0xFFh — 1.1 20.5 LSb MCP4716 , Code = 0x3FFh — 4.1 82.0 LSb MCP4726 , Code = 0xFFFh Gain Error (Note 2)
gE -2 -0.10 2 % of FSR MCP4706 , Code = 0xFFh VREF1:VREF0 = 00 , G = 0 -2 -0.10 2 % of FSR MCP4716 , Code = 0x3FFh VREF1:VREF0 = 00 , G = 0 -2 -0.10 2 % of FSR MCP4726 , Code = 0xFFFh VREF1:VREF0 = 00 , G = 0 Gain Error Drift ΔG/°C — -3 — ppm/°C Resolution n 8 bits MCP 10 bits MCP 12 bits MCP INL Error (Note 7)
INL -0.907 ±0.125 +0.907 LSb MCP4706 (codes: 6 to 250) -3.625 ±0.5 +3.625 LSb MCP4716 (codes: 25 to 1000) -14.5 ±2 +14.5 LSb MCP4726 (codes: 100 to 4000) DNL Error (Note 7)
DNL -0.05 ±0.0125 +0.05 LSb MCP4706 (codes: 6 to 250) -0.188 ±0.05 +0.188 LSb MCP4716 (codes: 25 to 1000) -0.75 ±0.2 +0.75 LSb MCP4726 (codes: 100 to 4000) Note 1: This parameter is ensured by design and is not 100% tested. 2: This Gain error does not include Offset error. See Section 1.0 “Electrical Characteristics” for more details in plots. 3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device). 4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V (^) DD over time. 5: This parameter is ensured by characterization, and not 100% tested. 6: The PD1:PD0 = 10 , and ‘ 11 ’ configurations should have the same current. 7: VDD = V (^) REF = 5.5V.
© 2011-2012 Microchip Technology Inc. DS22272C-page 5
Output Amplifier Minimum Output Voltage
VOUT(MIN) — 0.01 — V Output Amplifier’s minimum drive
Maximum Output Voltage
VOUT(MAX) — VDD –
— V Output Amplifier’s maximum drive
Phase Margin PM — 66 — Degree (°)
CL = 400 pF, RL = ∞
Slew Rate SR — 0.55 — V/μs Short Circuit Current I (^) SC 7 15 24 mA Settling Time tSETTLING — 6 — μs Note 3 Power-Down Output Disable Time Delay
T (^) PDD — 1 — μs PD1:PD0 = 00 -> 11 , ‘ 10 ’, or ‘ 01 ’ started from falling edge SCL at end of ACK bit. VOUT = VOUT - 10 mV. V (^) OUT not connected. Power-Down Output Enable Time Delay
T (^) PDE — 10.5 — μs PD1:PD0 = 11 , ‘ 10 ’, or ‘ 01 ’ -> “ 00 ” started from falling edge SCL at end of ACK bit. Volatile DAC Register = FFh, VOUT = 10 mV. V (^) OUT not connected. External Reference (V (^) REF ) (Note 1) Input Range V (^) REF 0.04 — VDD -
V Buffered mode
0 — VDD V Unbuffered mode Input Impedance RVREF — 210 — kΩ Unbuffered mode Input Capacitance C_REF — 29 — pF Unbuffered mode -3 dB Bandwidth — 86.5 — kHz V (^) REF = 2.048V ± 0.1V, VREF1:VREF0 = 10 , G = 0 — 67.7 — kHz VREF = 2.048V ± 0.1V, VREF1:VREF0 = 10 , G = 1 Total Harmonic Distortion
THD — -73 — dB V (^) REF = 2.048V ± 0.1V, VREF1:VREF0 = 10 , G = 0 , Frequency = 1 kHz Dynamic Performance (Note 1) Major Code Transition Glitch
— 45 — nV-s 1 LSb change around major carry (800h to 7FFh) Digital Feedthrough — <10 — nV-s
ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, V (^) DD = 2.7V to 5.5V, V (^) SS = 0V, R L = 5 kΩ from V (^) OUT to GND, CL = 100 pF, TA = -40°C to +125°C. Typical values at +25°C. Parameters Symbol Min Typical Max Units Conditions
Note 1: This parameter is ensured by design and is not 100% tested. 2: This Gain error does not include Offset error. See Section 1.0 “Electrical Characteristics” for more details in plots. 3: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit device). 4: The power-up ramp rate affects on uploading the EEPROM contents to the DAC register. It measures the rise of V (^) DD over time. 5: This parameter is ensured by characterization, and not 100% tested. 6: The PD1:PD0 = 10 , and ‘ 11 ’ configurations should have the same current. 7: VDD = V (^) REF = 5.5V.
© 2011-2012 Microchip Technology Inc. DS22272C-page 7
1.1 I^2 C Mode Timing Waveforms and Requirements
FIGURE 1-1: Power-On and Brown-Out Reset Waveforms.
FIGURE 1-2: I^2 C Power-Down Command Timing.
TABLE 1-1: RESET TIMING
Timing Characteristics
Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (extended) All parameters apply across the specified operating ranges unless noted. VDD = +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices. Typical specifications represent values for V (^) DD = 5.5V, TA = +25°C.
Parameters Sym Min Typ Max Units Conditions Power-Up Reset Delay
t (^) PORD — 60 — μs Monitor ACK bit response to ensure device responds to command. Brown-Out Reset Delay
t (^) BORD — 1 — μs VDD transitions from VDD(MIN) → > VPOR VOUT driven to VOUT disabled Power-Down Disable Time Delay
TPDD — 2.5 — μs VDD = 5V PD1:PD0 → 00 (from ‘ 01 ’, ‘ 10 ’, or ‘ 11 ’), from falling edge SCL at end of ACK bit. — 5 — μs V (^) DD = 3V PD1:PD0 → 00 (from ‘ 01 ’, ‘ 10 ’, or ‘ 11 ’), from falling edge SCL at end of ACK bit. Power-Down Enable Time Delay
T (^) PDE — 10.5 — μs PD1:PD0 → 01 , ‘ 10 ’, or ‘ 11 ’ (from ‘ 00 ’), from falling edge SCL at end of ACK bit.
V (^) DD
SDA
tPORD t (^) BORD
V (^) OUT
SCL VIH VIH
V (^) POR (VBOR )
V (^) OUT pulled down by internal 500 kΩ (typical) resistor
I 2 C™ Interface is operational
SDA
SCL
ACK Stop^ Start^ ACK
VOUT
tPDE tPDD
DS22272C-page 8 © 2011-2012 Microchip Technology Inc.
FIGURE 1-3: I^2 C Bus Start/Stop Bits Timing Waveforms.
TABLE 1-2: I^2 C BUS START/STOP BITS REQUIREMENTS
I 2 C™ AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Electrical Characteristics
Param. No.
Symbol Characteristic Min Max Units Conditions
F (^) SCL SCL pin Frequency Standard mode 0 100 kHz Cb = 400 pF, 2.7V - 5.5V Fast mode 0 400 kHz C (^) b = 400 pF, 2.7V - 5.5V High-Speed 1.7 0 1.7 MHz C (^) b = 400 pF, 4.5V - 5.5V High-Speed 3.4 0 3.4 MHz C (^) b = 100 pF, 4.5V - 5.5V D102 Cb Bus capacitive loading
100 kHz mode — 400 pF 400 kHz mode — 400 pF 1.7 MHz mode — 400 pF 3.4 MHz mode — 100 pF 90 TSU :STA Start condition 100 kHz mode 4700 — ns Only relevant for repeated Setup time 400 kHz mode 600 — ns Start condition 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns 91 T HD: STA Start condition 100 kHz mode 4000 — ns After this period, the first Hold time 400 kHz mode 600 — ns clock pulse is generated 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns 92 TSU :STO Stop condition 100 kHz mode 4000 — ns Setup time 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns 93 T HD: STO Stop condition 100 kHz mode 4000 — ns Hold time 400 kHz mode 600 — ns 1.7 MHz mode 160 — ns 3.4 MHz mode 160 — ns 94 T (^) HVCSU HVC to SCL Setup time 25 — uS High Voltage Commands 95 T (^) HVCHD SCL to HVC Hold time 25 — uS High Voltage Commands
SCL 91 93
SDA
Start Condition
Stop Condition
VIH
VIL
DS22272C-page 10 © 2011-2012 Microchip Technology Inc.
102A (5)^ T^ RSCL SCL rise time^ 100 kHz mode^ —^1000 ns^ C^ b is specified to be from 10 to 400 pF (100 pF maximum for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 80 ns
1.7 MHz mode 20 160 ns After a Repeated Start condition or an Acknowledge bit 3.4 MHz mode 10 40 ns 3.4 MHz mode 10 80 ns After a Repeated Start condition or an Acknowledge bit
102B (5)^ T^ RSDA SDA rise time^ 100 kHz mode^ —^1000 ns^ C^ b is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns
103A (5)^ T^ FSCL SCL fall time^ 100 kHz mode^ —^300 ns^ C^ b is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb 300 ns 1.7 MHz mode 20 80 ns 3.4 MHz mode 10 40 ns
103B (5)^ T^ FSDA SDA fall time^ 100 kHz mode^ —^300 ns^ C^ b is specified to be from 10 to 400 pF (100 pF max for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb (4)^ 300 ns 1.7 MHz mode 20 160 ns 3.4 MHz mode 10 80 ns
TABLE 1-3: I^2 C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I 2 C™ AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Electrical Characteristics
Param. No.
Sym Characteristic Min Max Units Conditions
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I 2 C™ bus device can be used in a Standard mode (100 kHz) I^2 C bus system, but the requirement t (^) SU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line. T (^) R max.+t (^) SU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I^2 C bus specification) before the SCL line is released. 3: The MCP47X6 device must provide a data hold time to bridge the undefined part between V (^) IH and V (^) IL of the falling edge of the SCL signal. This specification is not a part of the I 2 C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use Cb in pF for the calculations. 5: Not Tested. This parameter ensured by characterization. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I 2 C bus line. If this parameter is too long, the Data Input Setup (T (^) SU:DAT ) or Clock Low time (T (^) LOW ) can be affected. Data Input: This parameter must be longer than t (^) SP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. 7: Ensured by the TAA 3.4 MHz specification test. 8: The specification is not part of the I 2 C specification. TAA = T (^) HD:DAT + TFSDA (or TRSDA).
© 2011-2012 Microchip Technology Inc. DS22272C-page 11
106 T (^) HD:DAT Data input hold time
100 kHz mode 0 — ns 2.7V-5.5V, Note 6 400 kHz mode 0 — ns 2.7V-5.5V, Note 6 1.7 MHz mode 0 — ns 4.5V-5.5V, Note 6 3.4 MHz mode 0 — ns 4.5V-5.5V, Note 6 107 T (^) SU:DAT Data input setup time
100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 1.7 MHz mode 10 — ns 3.4 MHz mode 10 — ns 109 TAA Output valid from clock
100 kHz mode — 3750 ns Note 1, Note 8 400 kHz mode — 1200 ns 1.7 MHz mode — 150 ns Cb = 100 pF, Note 1 , Note 7, Note 8 — 310 ns Cb = 400 pF, Note 1 , Note 5, Note 8 3.4 MHz mode — 150 ns Cb = 100 pF, Note 1, Note 8 110 T BUF Bus free time 100 kHz mode 4700 — ns Time the bus must be free before a new transmission can start
400 kHz mode 1300 — ns 1.7 MHz mode N/A — ns 3.4 MHz mode N/A — ns
TABLE 1-3: I^2 C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I 2 C™ AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature -40°C ≤ TA ≤ +125°C (Extended) Operating Voltage VDD range is described in Electrical Characteristics
Param. No.
Sym Characteristic Min Max Units Conditions
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2: A Fast mode (400 kHz) I 2 C™ bus device can be used in a Standard mode (100 kHz) I^2 C bus system, but the requirement t (^) SU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output the next data bit to the SDA line. T (^) R max.+t (^) SU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I 2 C bus specification) before the SCL line is released. 3: The MCP47X6 device must provide a data hold time to bridge the undefined part between V (^) IH and V (^) IL of the falling edge of the SCL signal. This specification is not a part of the I 2 C specification, but must be tested in order to ensure that the output data will meet the setup and hold specifications for the receiving device. 4: Use Cb in pF for the calculations. 5: Not Tested. This parameter ensured by characterization. 6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do not unintentionally create a Start or Stop condition. If this parameter is too short, it can create an unintentional Start or Stop condition to other devices on the I 2 C bus line. If this parameter is too long, the Data Input Setup (T (^) SU:DAT ) or Clock Low time (T (^) LOW ) can be affected. Data Input: This parameter must be longer than t (^) SP. Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. 7: Ensured by the TAA 3.4 MHz specification test. 8: The specification is not part of the I 2 C specification. TAA = T (^) HD:DAT + TFSDA (or TRSDA).
© 2011-2012 Microchip Technology Inc. DS22272C-page 13
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Symbol Min Typical Max Units Conditions Temperature Ranges Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Note 1 Storage Temperature Range TA -65 — +150 °C Thermal Package Resistances Thermal Resistance, 6L-SOT-23 θJA — 190 — °C/W Thermal Resistance, 6L-DFN (2 x 2) θJA — 91 — °C/W Note 1: The MCP47X6 devices operate over this extended temperature range, but with reduced performance. Operation in this range must not cause T (^) J to exceed the Maximum Junction Temperature of +150°C.
DS22272C-page 14 © 2011-2012 Microchip Technology Inc.
NOTES:
DS22272C-page 16 © 2011-2012 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
FIGURE 2-7: DNL vs. Code (code = 100
to 4000) and Temperature ( MCP4726 ).
VDD = 5V, VREF1 :VREF0 = 00.
FIGURE 2-8: DNL vs. Code (code = 25 to
1000) and Temperature ( MCP4716 ).
VDD = 5V, VREF1 :VREF0 = 00.
FIGURE 2-9: DNL vs. Code (code = 6 to
250) and Temperature ( MCP4706 ).
VDD = 5V, VREF1 :VREF0 = 00.
FIGURE 2-10: DNL vs. Code (code = 100
to 4000) and Temperature ( MCP4726 ).
V DD = 2.7V, V REF1 :V REF0 = 00.
FIGURE 2-11: DNL vs. Code (code = 25 to
1000) and Temperature ( MCP4716 ).
V DD = 2.7V, V REF1 :V REF0 = 00.
FIGURE 2-12: DNL vs. Code (code = 6 to
250) and Temperature ( MCP4706 ).
V DD = 2.7V, V REF1 :V REF0 = 00.
-0.
-0.
-0.
-0.
0 1024 2048 3072 4096
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
-0.
-0.
-0.
0 128 256 384 512 640 768 896 1024
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
-0.
-0.
-0.
-0.
0 32 64 96 128 160 192 224 256
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
-0.
-0.
-0.
-0.
0 1024 2048 3072 4096
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
-0.
-0.
-0.
0 128 256 384 512 640 768 896 1024
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
-0.
-0.
-0.
-0.
0 32 64 96 128 160 192 224 256
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
© 2011-2012 Microchip Technology Inc. DS22272C-page 17
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
FIGURE 2-13: Zero-Scale Error (ZSE) vs.
VDD and Temperature ( MCP4726 ).
VREF1 :V REF0 = 00.
FIGURE 2-14: Zero-Scale Error (ZSE) vs.
VDD and Temperature ( MCP4716 ).
VREF1 :V REF0 = 00.
FIGURE 2-15: Zero-Scale Error (ZSE) vs.
VDD and Temperature ( MCP4706 ).
VREF1 :V REF0 = 00.
FIGURE 2-16: Full-Scale Error (FSE) vs.
V DD and Temperature ( MCP4726 ).
V REF1:V REF0 = 00.
FIGURE 2-17: Full-Scale Error (FSE) vs.
V DD and Temperature ( MCP4716 ).
V REF1:V REF0 = 00.
FIGURE 2-18: Full-Scale Error (FSE) vs.
V DD and Temperature ( MCP4706 ).
V REF1:V REF0 = 00.
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Zero Scale Error (LSb)
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Zero Scale Error (LSb)
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Zero Scale Error (LSb)
-32.
-30.
-28.
-26.
-24.
-22.
-20.
-18.
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Full Scale Error (LSb)
-8.
-7.
-6.
-5.
-4.
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Full Scale Error (LSb)
-2.
-1.
-1.
-0.
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Full Scale Error (LSb)
© 2011-2012 Microchip Technology Inc. DS22272C-page 19
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
FIGURE 2-25: DNL vs. Code (code = 100
to 4000) and Temperature ( MCP4726 ).
VDD = 5V, VREF1 :VREF0 = 10 , G = 0 ,
VREF = VDD.
FIGURE 2-26: DNL vs. Code (code = 25 to
1000) and Temperature ( MCP4716 ).
VDD = 5V, VREF1 :VREF0 = 10 , G = 0 ,
VREF = VDD.
FIGURE 2-27: DNL vs. Code (code = 6 to
250) and Temperature ( MCP4706 ).
VDD = 5V, VREF1 :VREF0 = 10 , G = 0 ,
VREF = VDD.
FIGURE 2-28: DNL vs. Code (code = 100
to 4000) and Temperature ( MCP4726 ).
V DD = 2.7V, V REF1 :V REF0 = 10 , G = 0 ,
V REF = VDD.
FIGURE 2-29: DNL vs. Code (code = 25 to
1000) and Temperature ( MCP4716 ).
V DD = 2.7V, V REF1 :V REF0 = 10 , G = 0 ,
V REF = VDD.
FIGURE 2-30: DNL vs. Code (code = 6 to
250) and Temperature ( MCP4706 ).
V DD = 2.7V, V REF1 :V REF0 = 10 , G = 0 ,
V REF = VDD.
-0.
-0.
-0.
-0.
0 1024 2048 3072 4096
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
-0.
-0.
-0.
0 128 256 384 512 640 768 896 1024
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
-0.
-0.
-0.
-0.
0 32 64 96 128 160 192 224 256
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
-0.
-0.
-0.
-0.
0 1024 2048 3072 4096
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
-0.
-0.
-0.
0 128 256 384 512 640 768 896 1024
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
-0.
-0.
-0.
-0.
0 32 64 96 128 160 192 224 256
-40C+25C +85C+125C
Volatile DAC Register Code
DNL Error (LSb)
DS22272C-page 20 © 2011-2012 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VRL = Internal, Gain = x1, RL = 5 kΩ, CL = 100 pF.
FIGURE 2-31: Zero-Scale Error (ZSE) vs.
Temperature ( MCP4726 ).
VDD = 5V, VREF1 :VREF0 = 10 , G = 0 ,
VREF = VDD.
FIGURE 2-32: Zero-Scale Error (ZSE) vs.
Temperature ( MCP4716 ).
VDD = 5V, VREF1 :VREF0 = 10 , G = 0 ,
VREF = VDD.
FIGURE 2-33: Zero-Scale Error (ZSE) vs.
Temperature ( MCP4706 ).
VDD = 5V, VREF1 :VREF0 = 10 , G = 0 ,
VREF = VDD.
FIGURE 2-34: Full-Scale Error (FSE) vs.
Temperature ( MCP4726 ).
V DD = 2.7V, V REF1 :V REF0 = 10 , G = 0 ,
V REF = VDD.
FIGURE 2-35: Full-Scale Error (FSE) vs.
Temperature ( MCP4716 ).
V DD = 2.7V, V REF1 :V REF0 = 10 , G = 0 ,
V REF = VDD.
FIGURE 2-36: Full-Scale Error (FSE) vs.
Temperature ( MCP4706 ).
V DD = 2.7V, V REF1 :V REF0 = 10 , G = 0 ,
V REF = VDD.
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Zero Scale Error (LSb)
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Zero Scale Error (LSb)
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Zero Scale Error (LSb)
-32.
-30.
-28.
-26.
-24.
-22.
-20.
-18.
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Full Scale Error (LSb)
-8.
-7.
-6.
-5.
-4.
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Full Scale Error (LSb)
-2.
-1.
-1.
-0.
-40 -20 0 20 40 60 80 100 120
2.7V5.0V 5.5V
Temperature (°C)
Full Scale Error (LSb)
