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Power MOSFET Basics
By Vrej Barkhordarian, International Rectifier, El Segundo, Ca.
Breakdown Voltage.........................................
On-resistance..................................................
Transconductance............................................
Threshold Voltage...........................................
Diode Forward Voltage..................................
Power Dissipation...........................................
Dynamic Characteristics................................
Gate Charge....................................................
dV/dt Capability...............................................
Power MOSFET Basics Vrej Barkhordarian, International Rectifier, El Segundo, Ca.
Discrete power MOSFETs employ semiconductor processing techniques that are similar to those of today's VLSI circuits, although the device geometry, voltage and current levels are significantly different from the design used in VLSI devices. The metal oxide semiconductor field effect transistor (MOSFET) is based on the original field-effect transistor introduced in the 70s. Figure 1 shows the device schematic, transfer characteristics and device symbol for a MOSFET. The invention of the power MOSFET was partly driven by the limitations of bipolar power junction transistors (BJTs) which, until recently, was the device of choice in power electronics applications.
Although it is not possible to define absolutely the operating boundaries of a power device, we will loosely refer to the power device as any device that can switch at least 1A. The bipolar power transistor is a current controlled device. A large base drive current as high as one-fifth of the collector current is required to keep the device in the ON state.
Also, higher reverse base drive currents are required to obtain fast turn-off. Despite the very advanced state of manufacturability and lower costs of BJTs, these limitations have made the base drive circuit design more complicated and hence more expensive than the power MOSFET.
Source Contact
Field Oxide
Gate Oxide
Gate Metallization
Drain Contact
n Drain*
p-Substrate
Channel
n Source t ox*
l
(^0) VT VGS
0
ID
(a)
(b)
ID
D SB (Channel or Substrate)
S
G
(c)
Figure 1. Power MOSFET (a) Schematic, (b) Transfer Characteristics, (c) Device Symbol.
Figure 3 shows schematic diagram and Figure 4 shows the physical origin of the parasitic components in an n-channel power MOSFET. The parasitic JFET appearing between the two body implants restricts current flow when the depletion widths of the two adjacent body diodes extend into the drift region with increasing drain voltage. The parasitic BJT can make the device susceptible to unwanted device turn-on and premature breakdown. The base resistance RB must be minimized through careful design of the doping and distance under the source region. There are several parasitic capacitances associated with the power MOSFET as shown in Figure 3. CGS is the capacitance due to the overlap of the source and the channel regions by the polysilicon gate
and is independent of applied voltage. C (^) GD consists of two parts, the first is the capacitance associated with the overlap of the polysilicon gate and the silicon underneath in the JFET region. The second part is
the capacitance associated with the depletion region immediately under the gate. CGD is a nonlinear
function of voltage. Finally, CDS, the capacitance associated with the body-drift diode, varies inversely with the square root of the drain-source bias. There are currently two designs of power MOSFETs, usually referred to as the planar and the trench designs. The planar design has already been introduced in the schematic of Figure 3. Two variations of the trench power MOSFET are shown Figure 5. The trench technology has the advantage of higher cell density but is more difficult to manufacture than the planar device.
Metal
C (^) GS
C (^) gsm LTO
C (^) GD C (^) GS1 R (^) Ch
R (^) B BJT
n-
p-
C (^) DS
JFET
R (^) EPI
n-
n-^ Epi Layer
n-^ Substrate Figure 4. Power MOSFET Parasitic Components.
BREAKDOWN VOLTAGE
Breakdown voltage,
BVDSS , is the voltage at which the reverse-biased body-drift diode breaks down and significant current starts to flow between the source and drain by the avalanche multiplication process, while the gate and source are shorted together. Current-voltage characteristics of a power MOSFET are shown in Figure 6. BVDSS is normally measured at 250μA drain current. For drain voltages below BVDSS and with no bias on the gate, no channel is formed under the gate at the surface and the drain voltage is entirely supported by the reverse-biased body-drift p-n junction. Two related phenomena can occur in poorly designed and processed devices: punch-through and reach-through. Punch- through is observed when the depletion region on the source side of the body-drift p-n junction reaches the source region at drain voltages below the rated avalanche voltage of the device. This provides a current path between source and drain and causes a soft breakdown characteristics as shown in Figure 7. The leakage current flowing between source and drain is denoted by IDSS. There are tradeoffs to be made between RDS(on) that requires shorter channel lengths and punch-through avoidance that requires longer channel lengths.
The reach-through phenomenon occurs when the depletion region on the drift side of the body-drift p-n junction reaches the epilayer-substrate interface before avalanching takes place in the epi. Once the depletion edge enters the high carrier concentration substrate, a further increase in drain voltage will
cause the electric field to quickly reach the critical value of 2x10 5 V/cm where avalanching begins.
Source Gate
Source
Gate Oxide
Channel
Oxide
n-^ Epi Layer
n+^ Substrate (100)
Drain (b)
S G S
Electron Flow
D (a)
Figure 5. Trench MOSFET (a) Current Crowding in V-Groove Trench MOSFET, (b) Truncated V-Groove MOSFET
Channel length also affects transconductance. Reduced channel length is beneficial to both gfs and on-resistance, with punch-through as a tradeoff. The lower limit of this length is set by the ability to control the double-diffusion process and is around 1-2mm today. Finally the lower the gate oxide thickness the higher gfs.
THRESHOLD VOLTAGE
Threshold voltage, V (^) th , is defined as the minimum gate electrode bias required to strongly invert the surface under the poly and form a conducting channel between
the source and the drain regions. V (^) th is usually measured at a drain-source current of 250μA. Common values are 2-4V for high voltage devices with thicker gate oxides, and 1-2V for lower voltage, logic-compatible devices with thinner gate oxides. With power MOSFETs finding increasing use in portable electronics and wireless communications where battery power is at a premium, the trend is toward lower values of RDS(on) and Vth.
DIODE FORWARD VOLTAGE
The diode forward voltage, VF, is the guaranteed maximum forward drop of the body-drain diode at a specified value of source current. Figure 10 shows a typical I-V characteristics for this diode at two temperatures. P- channel devices have a higher VF due to the higher contact resistance between metal and p-silicon compared with n-type silicon. Maximum values of 1.6V for high voltage devices (>100V) and 1.0V for low voltage devices (<100V) are common.
POWER DISSIPATION
The maximum allowable power dissipation that will raise the die temperature to the maximum allowable when the case temperature is held at 25 0 C is important. It is give by Pd where:
Tjmax = Maximum allowable temperature of the p-n junction in the device (normally 150^0 C or 175 0 C) R (^) thJC = Junction-to-case thermal impedance of the device.
DYNAMIC CHARACTERISTICS
Sharp
Soft
ID
BVDSS VDS
Figure 7. Power MOSFET Breakdown Characteristics
N+
R (^) SOURCE R^ CH P-BASE
R (^) A
R (^) J
R (^) D
R (^) SUB
N+ SUBSTRATE
SOURCE
GATE
DRAIN
Figure 8. Origin of Internal Resistance in a Power MOSFET.
P (^) d T j
R thJC
=
m ax 25- (2)
When the MOSFET is used as a switch, its basic function is to control the drain current by the gate voltage. Figure 11(a) shows the transfer characteristics and Figure 11(b) is an equivalent circuit model often used for the analysis of MOSFET switching performance.
The switching performance of a device is determined by the time required to establish voltage changes
across capacitances. RG is the distributed resistance of the gate and is approximately inversely
proportional to active area. L (^) S and L (^) D are source and drain lead inductances and are around a few tens of
nH. Typical values of input (Ciss ), output (Coss ) and reverse transfer (Crss) capacitances given in the data sheets are used by circuit designers as a starting point in determining circuit component values. The data sheet capacitances are defined in terms of the equivalent circuit capacitances as:
Voltage Rating: 50V 100V 500V
Packaging
Metallization Source
Channel
JFET Region
Expitaxial Layer
Substrate
R (^) EPI
R (^) CH
R (^) wcml
Figure 9. Relative Contributions to R (^) DS(on) With Different Voltage Ratings.
GATE CHARGE
Although input capacitance values are useful, they do not provide accurate results when comparing the switching performances of two devices from different manufacturers. Effects of device size and transconductance make such comparisons more difficult. A more useful parameter from the circuit design point of view is the gate charge rather than capacitance. Most manufacturers include both parameters on their data sheets. Figure 13 shows a typical gate charge waveform and the test circuit. When the gate is connected to the supply voltage,
VGS starts to increase until it
reaches Vth , at which point the drain current starts to flow and
the CGS starts to charge. During
the period t 1 to t 2 , CGS continues to charge, the gate voltage continues to rise and drain current rises proportionally. At time t 2 , CGS is completely charged and the drain current reaches the predetermined current I (^) D and stays constant while the drain voltage starts to fall. With reference to the equivalent
circuit model of the MOSFET shown in Figure 13, it can be seen that with CGS fully charged at t 2 , VGS
becomes constant and the drive current starts to charge the Miller capacitance, C (^) DG. This continues
until time t 3.
R (^) D
-
+
VDD
VDS
VGS
R (^) G
D.U.T.
-10V Pulse Width < 1 μμ s Duty Factor < 0.1%
(a)
Figure 12. Switching Time Test (a) Circuit, (b) VGS and VDS Waveforms
td(on) tr td(off) tf
VGS 100%
90%
VDS (b)
Charge time for the Miller capacitance is larger than that for the gate to source capacitance C (^) GS due to the rapidly changing
drain voltage between t 2 and t 3 (current = C
dv/dt). Once both of the capacitances C (^) GS
and C (^) GD are fully charged, gate voltage (VGS) starts increasing again until it reaches the
supply voltage at time t 4. The gate charge
(QGS + QGD) corresponding to time t 3 is the bare minimum charge required to switch the device on. Good circuit design practice dictates the use of a higher gate voltage than the bare minimum required for switching and therefore the gate charge used in the calculations is Q (^) G
corresponding to t 4.
The advantage of using gate charge is that the designer can easily calculate the amount of current required from the drive circuit to switch the device on in a desired length of time because Q = CV and I = C dv/dt, the Q = Time x current. For example, a device with a gate charge of 20nC can be turned on in 20μsec if 1ma is supplied to the gate or it can turn on in 20nsec if the gate current is increased to 1A. These simple calculations would not have been possible with input capacitance values.
dv/dt CAPABILITY
Peak diode recovery is defined as the maximum rate of rise of drain-source voltage allowed, i.e., dv/dt capability. If this rate is exceeded then the voltage across the gate-source terminals may become higher than the threshold voltage of the device, forcing the device into current conduction mode, and under certain conditions a catastrophic failure may occur. There are two possible mechanisms by which a dv/dt induced turn-on may take place. Figure 14 shows the equivalent circuit model of a power MOSFET, including the parasitic BJT. The first mechanism of dv/dt induced turn-on becomes active through the feedback action of the gate-drain capacitance, CGD. When a voltage ramp appears across the drain and source terminal of the device a current I 1 flows through the gate resistance, RG , by means of the gate-drain capacitance,
CGD. RG is the total gate resistance in the circuit and the voltage drop across it is given by:
When the gate voltage V (^) GS exceeds the threshold voltage of the device Vth , the device is forced into conduction. The dv/dt capability for this mechanism is thus set by:
VDD
ID D
D
G
S C (^) GS
C (^) DG
S ID
TEST CIRCUIT (a)
OGS OGD
GATE VOLTAGE
VG
VG(TH)
t 0 t 1 t 2 t 3 t (^4) t DRAIN CURRENT
DRAIN VOLTAGE
VDD ID
WAVEFORM (b)
Figure 13. Gate Charge Test (a) Circuit, (b) Resulting Gate and Drain Waveforms.
V I R R C
dv
dt
GS =^1 G = G GD
References:
"HEXFET Power MOSFET Designer's Manual - Application Notes and Reliability Data," International Rectifier "Modern Power Devices," B. Jayant Baliga "Physics of Semiconductor Devices," S. M. Sze "Power FETs and Their Applications," Edwin S. Oxner "Power MOSFETs - Theory and Applications," Duncan A. Grant and John Gower
