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© 2009 Microchip Technology Inc. DS80478A-page 1
The PIC18F2455/2550/4455/4550 family devices that you have received conform functionally to the current Device Data Sheet (DS39632 D ), except for the anoma- lies described in this document.
The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
The errata described in this document will be addressed in future revisions of the PIC18F2455/2550/4455/ silicon.
Data Sheet clarifications and corrections start on page 18, following the discussion of silicon issues.
The silicon revision level can be identified using the current version of MPLAB ®^ IDE and Microchip’s programmers, debuggers, and emulation tools, which are available at the Microchip corporate web site (www.microchip.com).
For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkit™ 3:
- Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/ debugger or PICkit™ 3.
- From the main menu in MPLAB IDE, select Configure>Select Device , and then select the target part number in the dialog box.
- Select the MPLAB hardware tool ( Debugger>Select Tool ).
- Perform a “Connect” operation to the device ( Debugger>Connect ). Depending on the devel- opment tool used, the part number and Device Revision ID value appear in the Output window.
The DEVREV values for the various PIC18F2455/2550/ 4455/4550 silicon revisions are shown in Table 1.
Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision ( B7 ).
Note: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance.
TABLE 1: SILICON DEVREV VALUES
Part Number Device ID(1)^
Revision ID for Silicon Revision (2)
A3 B4 B5 B6 B PIC18F2455 126Xh
2h 4h 5h 6h 7h
PIC18F2550 124Xh PIC18F4455 122Xh PIC18F4550 120Xh Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration memory space. They are shown in hexadecimal in the format “DEVID DEVREV”. 2: Refer to the “PIC18F2XXX/4XXX Family Flash Microcontroller Programming Specification” (DS39622) for detailed information on Device and Revision IDs for your specific device.
PIC18F2455/2550/4455/4550 Family
Silicon Errata and Data Sheet Clarification
DS80478A-page 2 © 2009 Microchip Technology Inc.
TABLE 2: SILICON ISSUE SUMMARY
Module Feature (^) NumberItem Issue Summary
Affected Revisions (1)
A3 B4 B5 B6 B
EUSART
Nine-Bit mode 1.^ Back-to-back timing transmit corruption^ X
Timer1/
Sixteen-Bit mode 2.^ Write to TMR1H/3H may lengthen duration^ X
MSSP Slave Transmit
- Slave transmit, 10 TCY not blocked X
Interrupts
Two-Cycle Instructions 4.^ Special considerations for interrupt context save^ X
ECCP
ECCPASE
Bit 5.^ Do not use bit-wise operations on ECCPASE^ X
ECCP Auto-Restart 6. Immediate restart upon shutdown source removal
X
ECCP
Special Event Trigger 7.^
Compare mode, Special Event Trigger not like PIC18F452 X ADC Offset Error 8. Offset greater than data sheet X BOR VBOR 9. ‘ 11 ’ setting below minimum operating voltage X
USB SIE IN Endpoint
- PKTDIS set, NAK, four extra bytes sent X
PORTD
RDPU
Control Bit 11.^ Access to PORTE causes RDPU to clear^ X
MSSP
Slave Addressing 12.^ I^
(^2) C™ slave address masking not implemented X
EUSART
BAUDCON
Register 13.^ RXDTP, TXCKP do not exist^ X
USB
Ping-Pong Buffer 14.^ Ping-Pong mode ‘^11 ’ not supported^ X
MSSP
SPI Slave mode 15.^ SPI slave write collision^ X MSSP SPI mode 16. SPI SDO output may change X MSSP I 2 C™ mode 17. I 2 C pins may not initialize properly X MSSP SPI mode 18. In SPI mode, do not poll BF bit X EUSART Async mode 19. Extra zero bytes in Async mode X EUSART Async mode 20. Data corruption in 9-bit Async full-duplex X
EUSART
Receive Buffer 21.^ RCREG not valid for subsequent reads^ X
EUSART
Auto Wake-up 22.^ WUE bit not clearing promptly^ X Timer1/3 16-Bit Async 23. 16-Bit Async mode, TMR1H/3H not updated X Reset RAM 24. Asynch Reset can alter RAM X ECCP PWM mode 25. Dead-band delay incorrect X X X X X
MSSP
SPI Master mode 26.^
SPI master, write collision for FOSC/64 and Timer2/2 X^ X^ X^ X^ X MSSP I 2 C mode 27. Unaddressed I 2 C slave node may respond X EUSART Auto-Baud 28. Auto-baud sometimes does not work X
ADC
2 TOSC or RC Clock 29.^ EIL, EDL^ , not meeting data sheet at 511/512^ X^ X^ X Note 1: Only those issues indicated in the last column apply to the current silicon revision.
DS80478A-page 4 © 2009 Microchip Technology Inc.
Silicon Errata Issues
1. Module: EUSART
When performing back-to-back transmission in 9-bit mode (TX9D bit in the TXSTA register is set), an ongoing transmission’s timing can be corrupted if the TX9D bit (for the next transmis- sion) is not written immediately following the setting of TXIF. This is because any write to the TXSTA register results in a reset of the Baud Rate Generator which will effect any ongoing transmission.
Work around Load TX9D just after TXIF is set, either by polling TXIF or by writing TX9D at the beginning of the Interrupt Service Routine, or only write to TX9D when a transmission is not in progress (TRMT = 1 ).
Affected Silicon Revisions
2. Module: Timer1/
When Timer1/3 is operating in 16-bit mode and the prescale setting is not 1:1, a write to the TMR1H/TMR3H Buffer registers may lengthen the duration of the period between the incre- ments of the timer for the period in which TMR1H/TMR3H were written.
Work around Either of two work arounds can be used:
- Stop Timer1/Timer3 before writing the TMR1H/TMR3H registers
- Write TMR1L/TMR3L immediately after writing TMR1H/TMR3H
Affected Silicon Revisions
3. Module: MSSP
In Slave Transmit mode, when a transmission is initiated, the SSPBUF register may be written for up to 10 TCY before additional writes are blocked. The data transfer may be corrupted if SSPBUF is written during this time. The WCOL bit is set any time an SSPBUF write occurs during a transfer.
Work around Avoid writing SSPBUF until the data transfer is complete, indicated by the setting of the SSPIF bit (PIR1<3>). To ensure any potential transfer in progress is not corrupted, verify that the WCOL bit (SSPCON1<7>) is clear after writing SSPBUF.
Affected Silicon Revisions
Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision ( B7 ).
A3 B4 B5 B6 B
X
A3 B4 B5 B6 B
X
A3 B4 B5 B6 B
X
© 2009 Microchip Technology Inc. DS80478A-page 5
4. Module: Interrupts
If an interrupt occurs during a two-cycle instruc- tion that modifies the STATUS, BSR or WREG register, the unmodified value of the register will be saved to the corresponding Fast Return (Shadow) register and upon a fast return from the interrupt, the unmodified value will be restored to the STATUS, BSR or WREG register. For example, if a high-priority interrupt occurs during the instruction, “MOVFF TEMP, WREG”, the MOVFF instruction will be completed and WREG will be loaded with the value of TEMP before branching to ISR. However, the previous value of WREG will be saved to the Fast Return register during ISR branching. Upon return from the interrupt with a fast return, the previous value of WREG in the Fast Return register will be written to WREG. This results in WREG containing the value it had before execution of “MOVFF TEMP, WREG“. Affected instructions are:
Work around Alternative work arounds are available for the Assembly Language Programming and the C Programming Language:
Assembly Language Programming
Either of two work arounds can be used:
- If any two-cycle instruction is used to modify the WREG, BSR or STATUS register, do not use the RETFIE FAST instruction to return from the interrupt. Instead, save/restore WREG, BSR and STATUS via software per Example 9-1 in the Device Data Sheet. Alternatively, in the case of MOVFF, use the MOVF instruction to write to WREG instead. For example, use:
- As another alternative, use the work around shown in Example 1. This example overwrites the Fast Return register by making a dummy call to Foo with the fast option in the high-priority service routine.
EXAMPLE 1: INTERRUPT WORK AROUND – ASSEMBLY
MOVFF Fs, Fd Where Fd is WREG, BSR or STATUS MOVSF Zs, Fd Where Fd is WREG, BSR or STATUS MOVSS [Zs], [Zd] Where the destination is WREG, BSR or STATUS
MOVF TEMP, W
MOVWF BSR
instead of: MOVFF TEMP, BSR.
ISR @ 0x CALL Foo, FAST; store current value of WREG, BSR, STATUS for a second time Foo: POP ; clears return address of Foo call : ; insert high priority ISR code here : RETFIEFAST
© 2009 Microchip Technology Inc. DS80478A-page 7
5. Module: ECCP
When monitoring a shutdown condition using a bit test on the ECCPASE bit (ECCP1AS<7>) or performing a bit operation on the ECCPASE bit, the device may produce unexpected results.
Work around Before performing a bit test or bit operation on the ECCPASE bit, copy the ECCP1AS register to the working register and perform the operation there. By avoiding these operations on the ECCPASE bit in the ECCP1AS register, the module will operate normally. In Example 4, ECCPASE bit operations are performed on the W register.
EXAMPLE 4: ECCPASE OPERATION
Affected Silicon Revisions
6. Module: ECCP
When the CCP1 auto-shutdown feature is config- ured for automatic restart (PRSEN bit (ECCP1DEL<7>) = 1 ), the pulse terminates immediately in a shutdown event. In addition, the pulse may restart within the period, if the shut- down condition expires. This may result in the generation of short pulses on the PWM output(s).
Work around Configure the auto-shutdown for software restart by clearing the PRSEN bit (ECCP1DEL<7>). The PWM can be re-enabled, after the shutdown condition expires, by clearing the ECCPASE bit (ECCP1AS<7>).
Affected Silicon Revisions
7. Module: ECCP
When operating either Timer1 or Timer3 as a counter with a prescale value other than 1:1 and operating the ECCP in Compare mode with the Special Event Trigger (CCP1CON bits, CCP1M<3:0> = 1011 ), the Special Event Trigger Reset of the timer occurs as soon as there is a match between TMRxH:TMRxL and CCPR1H:CCPR1L. This differs from the PIC18F452, where the Special Event Trigger Reset of the timer occurs on the next rollover of the prescale counter after the match between TMRxH:TMRxL and CCPR1H:CCPR1L.
Work around To achieve the same timer Reset period on the PIC18F4550 family as the PIC18F452 family for a given clock source, add 1 to the value in CCPR1H:CCPR1L. In other words, if CCPR1H:CCPR1L = x for the PIC18F452, to achieve the same Reset period on the PIC18F4550 family, CCPR1H:CCPR1L = x + 1, where the prescale is 1, 2, 4 or 8 depending on the T1CKPS<1:0> bit values.
Affected Silicon Revisions
A3 B4 B5 B6 B
X
A3 B4 B5 B6 B
X
MOVF ECCP1AS, W
BTFSC WREG, ECCPASE
BRA SHUTDOWN_ROUTINE
A3 B4 B5 B6 B
X
DS80478A-page 8 © 2009 Microchip Technology Inc.
8. Module: A/D
The A/D offset is greater than the specified limit in Table 28-8 of the Device Data Sheet. The updated conditions and limits are shown in bold text in Table 28-8.
Work around Any of three work arounds may be used.
- Configure the A/D to use the VREF + and VREF - pins for the voltage references. This is done by setting the VCFG<1:0> bits (ADCON1<5:4>).
- Perform a conversion on a known voltage reference voltage and adjust the A/D result in software.
- Increase system clock speed to 48 MHz and adjust A/D settings accordingly. Higher system clock frequencies decrease offset error.
TABLE 28-8: A/D CONVERTER CHARACTERISTICS:PIC18F2455/2550/4455/4550 (INDUSTRIAL)
PIC18LF2455/2550/4455/4550 (INDUSTRIAL)
Affected Silicon Revisions
9. Module: DC Characteristics (BOR)
When the trip point for BORV<1:0> = 11 , the val- ues for parameter D005 (V BOR) in Section 28. “DC Characteristics” of the Device Data Sheet are not applicable as the device may reset below the minimum operating voltage for the device.
Work around None.
Affected Silicon Revisions
10. Module: USB
When an IN endpoint is owned by USB SIE and the UCON register’s PKTDIS bit is set, if a USB NAK event occurs on the IN endpoint before the PKTDIS bit is clear, then after the PKTDIS is clear, the pending IN endpoint will send out more bytes than expected. For example, if configured to send out 8 bytes, the SIE would actually send out 12 bytes of data.
Work around The PKTDIS bit is set when a USB control transfer setup packet is received. Clear this bit as soon as possible, particularly before turning over any IN endpoint ownership to the SIE.
Affected Silicon Revisions
Param No. Symbol^ Characteristic^ Min^ Typ^ Max^ Units^ Conditions
A06A E OFF Offset Error — — < ± 2.0 LSb VREF = VREF + and VREF - A06 EOFF Offset Error — — < ± 3.5 LSb VREF = VSS and VDD
A3 B4 B5 B6 B
X
A3 B4 B5 B6 B
X
A3 B4 B5 B6 B
X
DS80478A-page 10 © 2009 Microchip Technology Inc.
17. Module: MSSP
It has been observed that following a Power-on Reset, the I 2 C mode may not initialize properly by just configuring the SCL and SDA pins as either inputs or outputs. This has only been seen in a few unique system environments. A test of a statistically significant sample of pre- production systems, across the voltage and current range of the application's power supply, should indicate if a system is susceptible to this issue.
Work around Before configuring the module for I 2 C operation:
- Configure the SCL and SDA pins as outputs by clearing their corresponding TRIS bits.
- Force SCL and SDA low by clearing the corresponding LAT bits.
- While keeping the LAT bits clear, configure SCL and SDA as inputs by setting their TRIS bits. Once this is done, use the SSPCON1 and SSPCON2 registers to configure the proper I^2 C mode as before.
Affected Silicon Revisions
18. Module: MSSP
When the MSSP is configured for SPI mode, the Buffer Full bit, BF (SSPSTAT<0>), should not be polled in software to determine when the transfer is complete.
Work around Copy the SSPSTAT register into a variable and perform the bit test on the variable. In Example 5, SSPSTAT is copied into the working register where the bit test is performed.
EXAMPLE 5: SSPSTAT WORK AROUND
A second option is to poll the Master Synchronous Serial Port Interrupt Flag bit, SSPIF (PIR1<3>). This bit can be polled and will set when the transfer is complete.
Affected Silicon Revisions
A3 B4 B5 B6 B
X
A3 B4 B5 B6 B
X
loop_MSB: MOVF SSPSTAT, W BTFSS WREG, BF BRA loop_MSB
© 2009 Microchip Technology Inc. DS80478A-page 11
19. Module: EUSART
In rare situations, one or more extra zero bytes have been observed in a packet transmitted by the module operating in Asynchronous mode. The actual data is not lost or corrupted; only unwanted (extra) zero bytes are observed in the packet. This situation has only been observed when the contents of the transmit buffer, TXREG, are trans- ferred to the TSR during the transmission of a Stop bit. For this to occur, three things must happen in the same instruction cycle:
- TXREG is written to
- The baud rate counter overflows (at the end of the bit period)
- A Stop bit is being transmitted (shifted out of TSR)
Work around If possible, do not use the module’s double-buffer capability. Instead, load the TXREG register when the TRMT bit (TXSTA<1>) is set, indicating the TSR is empty. If double-buffering is used and back-to-back transmission is performed, load TXREG immedi- ately after TXIF is set, or wait 1 bit time after TXIF is set. Both solutions prevent writing TXREG while a Stop bit is transmitted. The TXIF bit is set at the beginning of the Stop bit transmission. If transmission is intermittent, do one of the following:
- Wait for the TRMT bit to be set before loading TXREG
- Use a free timer resource to time the baud period. Set up the timer to overflow at the end of a Stop bit, then start the timer when you load the TXREG. Do not load the TXREG when timer is about to overflow.
Affected Silicon Revisions
20. Module: EUSART
In 9-Bit Asynchronous Full-Duplex Receive mode, the received data may be corrupted if the TX9D bit (TXSTA<0>) is not modified immediately after the RCIDL bit (BAUDCON<6>) is set.
Work around Write to TX9D only when a reception is not in progress (RCIDL = 1 ). Since there is no interrupt associated with RCIDL, it must be polled in software to determine when TX9D can be updated.
Affected Silicon Revisions
21. Module: EUSART
After the last received byte has been read from the EUSART receive buffer (RCREG), the value is no longer valid for subsequent read operations.
Work around The RCREG register should only be read once for each byte received. After each byte is received from the EUSART, store the byte in a user variable. To determine when a byte is available to read from RCREG, poll the RCIDL bit (BAUDCON<6>) for a low-to-high transition, or use the EUSART Receive Interrupt Flag, RCIF (PIR1<5>).
Affected Silicon Revisions
A3 B4 B5 B6 B
X
A3 B4 B5 B6 B
X
A3 B4 B5 B6 B
X
© 2009 Microchip Technology Inc. DS80478A-page 13
26. Module: MSSP
With MSSP in SPI Master mode, F OSC/64 or Timer2/2 clock rate and CKE = 0 , a write collision may occur if SSPBUF is loaded immediately after the transfer is complete. A delay may be required after the MSSP Interrupt Flag bit (SSPIF) is set or the Buffer Full bit (BF) is set – before writing SSPBUF. If the delay is insufficiently short, a write collision may occur as indicated by the WCOL bit being set.
Work around Add a software delay of one SCK period after detecting the completed transfer and prior to updating the SSPBUF contents.
Affected Silicon Revisions
27. Module: MSSP
In an I 2 C system with multiple slave nodes, an unaddressed slave may respond to bus activity when data on the bus matches its address. The first occurrence will set the BF bit. The second occurrence will set the BF and SSPOV bits. In both situations, the SSPIF bit is not set and an interrupt will not occur. The device will vector to the Interrupt Service Routine only if the interrupt is enabled and an address match occurs.
Work around The I 2 C slave must clear the SSPOV bit after each I 2 C event to maintain normal operation.
Affected Silicon Revisions
28. Module: EUSART
The EUSART auto-baud feature may periodically measure the incoming baud rate incorrectly. The rate of incorrect baud-rate measurements will depend on the frequency of the incoming synchronization byte and the system clock frequency.
Work around None.
Affected Silicon Revisions
29. Module: A/D
When the A/D clock source is selected as 2 TOSC or RC (when ADCS<2:0> = 000 or x11), in extremely rare cases, the E IL (Integral Linearity Error) and EDL (Differential Linearity Error) may exceed the data sheet specification at codes 511 and 512 only.
Work around Select a different A/D clock source (4 TOSC, 8 TOSC, 16 TOSC, 32 TOSC, 64 TOSC) and avoid selecting the 2 TOSC or RC modes.
Affected Silicon Revisions
30. Module: Resets (BOR)
If either the HLVD or USB modules are enabled, clearing the SBOREN bit (RCON<6>) when the soft- ware controlled BOR feature is enabled (BOREN<1:0> = 01 ) may cause a Brown-out Reset (BOR) event.
Work around Before clearing the SBOREN bit, temporarily disable the HLVD and USB modules.
Affected Silicon Revisions
A3 B4 B5 B6 B
X X X X X
A3 B4 B5 B6 B
X
A3 B4 B5 B6 B
X
A3 B4 B5 B6 B
X X X
A3 B4 B5 B6 B
X
DS80478A-page 14 © 2009 Microchip Technology Inc.
31. Module: MSSP
When operated in I 2 C™ Master mode, the I 2 C baud rate may be somewhat slower than predicted by the following formula:
Work around If the target application is sensitive to the baud rate and requires more precision, the SSPADD value can be adjusted to compensate. If this work around is going to be used, it is recom- mended that the firmware first check the Revision ID by reading the DEVID1 value at address, 3FFFFEh. Silicon revisions, B6 and B7, will match the I 2 C baud rate predicted by the given formula.
Affected Silicon Revisions
32. Module: MSSP
In SPI Slave mode with slave select enabled (SSPM<3:0> = 0100 ), the minimum time between the falling edge of the SS pin and first SCK edge is greater than specified in parameter 70 in Table 28-17 and Table 28-18. The updated specification is shown in bold in Table 3. The minimum time between SS pin low and an SSPBUF write is also 3 TCY. If the falling edge of the SS pin occurs greater than 3 TCY, before the first SCK edge or loading SSPBUF, the peripheral will function correctly. Also, if SSPBUF is written prior to the SS pin going low, the peripheral will function correctly.
TABLE 3: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING)
Work around None.
Affected Silicon Revisions
A3 B4 B5 B6 B
X X X
I 2 C Master mode, clock
F OSC
4 • ( SSPADD + 1 )
Param No.
Symbol Characteristic Min Max Units Conditions
70 TSSL2SC H,
TSSL2SC L
SS ↓ to SCK ↓ or SCK ↑ Input 3 TCY — ns
A3 B4 B5 B6 B
X X X X
DS80478A-page 16 © 2009 Microchip Technology Inc.
38. Module: MSSP
If the application firmware is expecting to receive valid data, in either SPI Slave or Master mode, the firmware must read from the SSPBUF register before writing the next byte to transmit to SSPBUF. If the firmware does not read from SSPBUF, the BF bit (SSPSTAT<0>) can still be set from the pre- vious transaction. If the BF bit is set, the incoming data byte is blocked from transferring from the SSPSR Shift register to the SSPBUF register. If the firmware then reads from SSPBUF, the data read will not match the data most recently received on the SDI pin.
In earlier silicon revisions (A3, B4 and B5), incom- ing data bytes received on the SDI pin are always transferred from SSPSR to SSPBUF, regardless of the state of the BF bit.
Work around If the firmware expects to receive valid data, always clear the BF bit by reading from SSPBUF prior to writing to SSPBUF, even when the current data in SSPBUF is not important. Sample work around code, suitable for all silicon revisions, is given in Example 7 (Assembly language) and Example 8 (C language).
Affected Silicon Revisions
EXAMPLE 7: SAMPLE ASSEMBLY CODE FOR TRANSFERRING SPI DATA
EXAMPLE 8: SAMPLE C CODE FOR TRANSFERRING SPI DATA
A3 B4 B5 B6 B
X X
WriteSPI: BCF PIR1, SSPIF MOVF SSPBUF, w ;Perform read, even if the data in SSPBUF is not important MOVLW 0xA5 ;In this example, let’s send “0xA5” to the other SPI device. MOVWF SSPBUF
WaitXmitComplete: BTFSS PIR1, SSPIF BRA WaitXmitComplete
MOVF SSPBUF, w ;The data received should be valid.
unsigned char WriteSPI(unsigned char ByteToSend) { unsigned char TempVariable;
PIR1bits.SSPIF = 0; TempVariable = SSPBUF; // Reads from SSPBUF, ensures BF bit is clear before SSPBUF = ByteToSend; // sending the next byte.
while(!PIR1bits.SSPIF); // Wait until the transmission is complete. return SSPBUF; // The data received should be valid. }
© 2009 Microchip Technology Inc. DS80478A-page 17
39. Module: MSSP (I^2 C™ Slave)
When configured for I 2 C™ slave reception, the MSSP module may not receive the correct data, in extremely rare cases. This occurs only if the Serial Receive/Transmit Buffer Register (SSPBUF) is not read after the SSPIF interrupt (PIR1<3>) has occurred, but before the first rising clock edge of the next byte being received.
Work around The issue can be resolved in either of these ways:
- Prior to the I 2 C slave reception, enable the clock stretching feature. This is done by setting the SEN bit (SSPCON2<0>).
- Each time the SSPIF is set, read the SSPBUF before the first rising clock edge of the next byte being received.
Affected Silicon Revisions
40. Module: MSSP (I^2 C™ Master)
When in I 2 C Master mode, if the slave performs clock stretching, the first clock pulse after the slave releases the SCL line may be narrower than the configured clock width. This may result in the slave missing the first clock in the next transmission/ reception.
Work around The clock pulse will be the normal width if the slave does not perform clock stretching.
Affected Silicon Revisions
41. Module: EUSART
In rare situations, when interrupts are enabled, unexpected results may occur if:
- The EUSART is disabled (the SPEN bit, RCSTAx<7> = 0 )
- The EUSART is re-enabled (RCSTAx<7> = 1 )
- A two-cycle instruction is executed immediately after setting SPEN = 1
Work around Add a 2 TCY delay after any instruction that re- enables the EUSART module (sets SPEN = 1 ). See Example 9.
EXAMPLE 9: RE-ENABLING A EUSART MODULE
Affected Silicon Revisions
A3 B4 B5 B6 B
X X X X X
A3 B4 B5 B6 B
X X
;Initial conditions: SPEN = 0 (module disabled) ;To re-enable the module: ;Re-Initialize TXSTAx, BAUDCONx, SPBRGx, SPBRGHx registers (if needed) ;Re-Initialize RCSTAx register (if needed), but do not set SPEN = 1 yet
;Now enable the module, but add a 2-Tcy delay before executing any two-cycle ;instructions bsf RCSTA1, SPEN ;or RCSTA2 if EUSART nop ;1 Tcy delay nop ;1 Tcy delay (two total)
;CPU may now execute 2 cycle instructions
A3 B4 B5 B6 B
X X X X
© 2009 Microchip Technology Inc. DS80478A-page 19
2. Module: Timer
The following text, Section 12.7 “Considerations in Asynchronous Counter Mode” , is new. It defines the proper method to update the TMR registers in Asynchronous mode. Section 12.7 is located after Section 12.6 “Using Timer1 as a Real-Time Clock” in the data sheet.
12.7 Considerations in Asynchronous
Counter Mode
Following a Timer1 interrupt and an update to the TMR1 registers, the Timer1 module uses a falling edge on its clock source to trigger the next register update on the rising edge. If the update is completed after the clock input has fallen, the next rising edge will not be counted.
If the application can reliably update TMR1 before the timer input goes low, no additional action is needed. Otherwise, an adjusted update can be performed fol- lowing a later Timer1 increment. This can be done by monitoring TMR1L within the interrupt routine until it increments, and then updating the TMR1H:TMR1L reg- ister pair while the clock is low, or one-half of the period of the clock source. Assuming that Timer1 is being used as a Real-Time Clock, the clock source is a 32.768 kHz crystal oscillator; in this case, one-half period of the clock is 15.25 μs.
The Real-Time Clock application code in Example 12- shows a typical ISR for Timer1, as well as the optional code required if the update cannot be done reliably within the required interval.
(Example 12-1 appears on page 18 of this errata.)
3. Module: Universal Serial Bus (USB)
In Section 17.2.2.8 “Internal Regulator,” the fol- lowing corrections should be noted (changes and added text appear in bold for the purposes of this errata):
- In the second paragraph, the first sentence is corrected to read, “The regulator is dis abled by default and can be en abled through the VREGEN Configuration bit.” The sentence originally stated, “The regulator is enabled by default and can be disabled through the VREGEN Configuration bit.”
- In the final note box of the section, Note 2 is corrected to read, “V DD must be greater than or equal to VUSB at all times, even with the regulator disabled.” The sentence originally stated, “V DD must be greater than VUSB at all times, even with the regulator disabled.”
4. Module: Master Synchronous Serial Port
(MSSP)
In Section 19.3.5 “Master Mode,” the second paragraph of the second column is corrected to read, “This allows a maximum data rate (at 48 MHz) of 12.00 Mbps.” The sentence originally stated, “This allows a maximum data rate (at 48 MHz) of 2.00 Mbps.”
5. Module: 10-Bit Analog-to-Digital (A/D)
Converter
In Register 21-1 , the display and the detailed bit description for bit 5 is corrected to “VCFG1” , rather than “VCFG0”. All other bit 5 displays and descriptions are correct in the Device Data Sheet.
6. Module: Special Features of the CPU
In Section 25.9.1 “Dedicated ICD/ICSP Port” , the second sentence of the fourth paragraph is corrected to state, “When VIHH is seen on the MCLR/VPP/RE3 pin, the state of the ICRST/ICVPP pin is ignored”. This refers to the high-voltage programming voltage level for ICSP™ (DC Specification D110). The sentence originally stated, “When VIH is seen on the MCLR/VPP/RE3 pin, the state of the ICRST/ ICVPP pin is ignored”. That incorrectly referred to the maximum input voltage tolerated by the pin as an I/O (DC specification D040).
DS80478A-page 20 © 2009 Microchip Technology Inc.
7. Module: Electrical Characteristics
In Section 28.3 “DC Characteristics,” pin- specific variations of parameters, D031 (Input Low Voltage) and D041 (Input High Voltage), are cor- rected as characteristic for pins, RB0 and RB1 , not pins, RC3 and RC4. The following relevant portion of the table indicates the corrections. (For clarity, the corrected items appear in bold text – all other text appears in plain text for purposes of this errata.)
8. Module: Electrical Characteristics
In Table 28-1 , the symbol for parameter D110 is corrected to VIHH , rather than V PP. The following relevant portion of Table 28-1 indi- cates the correction. (For clarity, the corrected item appears in bold text – all other text appears in plain text for purposes of this errata.)
TABLE 28-9: MEMORY PROGRAMMING REQUIREMENTS (PARTIAL PRESENTATION)
28.3 DC Characteristics: PIC18F2455/2550/4455/4550 (Industrial)
PIC18LF2455/2550/4455/4550 (Industrial) (Partial Presentation)
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial
Param No.
Symbol Characteristic Min Max Units Conditions
VIL Input Low Voltage D with Schmitt Trigger buffer RB0 and RB
VSS
VSS
0.2 VDD
0.3 VDD
V
V
VIH Input High Voltage D with Schmitt Trigger buffer RB0 and RB
0.8 VDD
0.7 VDD
VDD
VDD
V
V
DC Characteristics
Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param No. Sym^ Characteristic^ Min^ Typ
(†) (^) Max Units Conditions
Internal Program Memory Programming Specifications(1) D110 (^) VIHH Voltage on MCLR/VPP/RE3 pin 9.00 — 13.25 V (Note 2) † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: These specifications are for programming the on-chip program memory through the use of table write instructions. 2: Required only if Single-Supply Programming is disabled.
