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REV
[9] SOC: MEMORY PARTITION E1 & E
6. TRANSIMITTER NAME USED AS PREFIX WITH RX AND TX CONNECTIONS
12.SUFFIX _P FOR P JUNCTION
15.PWRGD FOR POWER GOOD
16.REV AND FAB ARE SET USING CUSTOM VARIABLES
CACTUS
FAB G RETAIL
[49] HDMI LOAD SWITCHES
[50] CONN: ODD & HDD
[4] SOC: POWER: MEMIO,CPUCORE,NBCORE,MISC [51] CONN: FRONT PANEL, FAN, AUDIO
[3] SOC: VIDEO
[12] SOC: MEMORY PARTITION B1 & B
[70] I2C
[71] MARGIN: SOCPHY,SOC1P8,MEMIO,NBCORE
[72] MONITOR: VSOC1P8, VSOCPHY, V12P
[73] CONN: FACET BOARD
[74] CONN: SWITCHES
[79] DEBUG: VR HEADERS, TEST POINTS, CONNECTORS
[80] LABELS AND MOUNTING
5. LANED SIGNALS ARE GROUPED ON SYMBOLS
[47] CONN: HDMI IN
[46] CONN: WIFI
[45] CONN: USB (FRONT & REAR)
[44] CONN: RJ45,TOSLINK
[43] EMMC MEMORY
[42] ETHERNET CONTROLLER
[41] KIC: DECOUPLING
[27] MEMORY: CHANNEL C/D DECOUPLING
[26] MEMORY: CHANNEL D
[25] MEMORY: CHANNEL D
[67] VREGS: V1P1 STANDBY, V1P8 STANDBY
[66] VREGS: V3P3 STANDBY
[65] VREGS: V_SB1P8, V_SB1P
1. MSB TO LSB IS TOP TO BOTTOM
3. ORDER OF PAGES=CHIP INTERFACES, TERMINATION, POWER, DECOUPLING
7. SUFFIX V_ IS USED FOR VOLTAGE RAIL SIGNAL NAMES
8. SUFFIX _DP AND _DN ARE USED FOR DIFFERIENTAL PAIRS
9. UNNAMED NETS ARE NAMED WITH /2 TEXT SIZE
10.SUFFIX _N FOR ACTIVE LOW OR N JUNCTION
13.SUFFIX _EN FOR ENABLE
[7] SOC: POWER: VSS
[13] SOC: MEMORY PARTITION A1 & A
[40] KIC: POWER RULES: (APPLIED WHEN POSSIBLE)
[55] VREGS: GFXCORE OUTPUT PHASE 1 & 2
14.'CLK' FOR CLOCKS, 'RST' FOR RESETS
[82] BOM DEFINITIONS
[68] STANDBY GATES
[69] IR BLASTER
[33] MEMORY: ADDITIONAL DECOUPLING
[22] MEMORY: CHANNEL A/B DECOUPLING
[53] VREGS: INPUT FILTERS
[8] SOC: MEMORY PARTITION F1 & F
[11] SOC: MEMORY PARTITION C1 & C
[14] SOC: DEBUG, SB SIGNALS, V_BAT
[18] MEMORY: CHANNEL A
[30] MEMORY: CHANNEL F
[63] VREGS: V3P3, VSOC1P
[64] VREGS: VSOCPHY/VFUSE
[61] VREGS: NBCORE
[23] MEMORY: CHANNEL C
[78] PREMIUM SPEAKER (SE/LE)
[15] SOC: DECOUPLING
[16] SOC: DECOUPLING
[48] CONN: HDMI OUT
[38] KIC: POWER
[54] VREGS: CPUCORE & GFXCORE
[6] SOC: POWER: VSS
[60] VREGS: MEMIO OUTPUT
[28] MEMORY: CHANNEL E
[10] SOC: MEMORY PARTITION D1 & D
[19] MEMORY: CHANNEL A
[39] KIC: CLOCKS, STRAPPING, POR
[52] CONN: POWER
CONTENTS
[77] CLOCK BUFFER
[62] VREGS: V5P
2. WHEN POSSIBLE: INPUTS ON LEFT, OUTPUTS ON RIGHT
[1] COVER PAGE
[17] SOC: DECOUPLING
PAGE
[21] MEMORY: CHANNEL B
[2] SOC: PCIEX,CLOCKS
[20] MEMORY: CHANNEL B
[29] MEMORY: CHANNEL E
[31] MEMORY: CHANNEL F
[32] MEMORY: CHANNEL E/F DECOUPLING
[37] KIC: FACET
[36] KIC: SMC
[35] KIC: PCIEX, SATA, VIDEO
[34] KIC: USB
[75] CONN: HDT
[76] CONN: M.
[81] FRONT PANEL USB - NESTED PCB
4. AVOID USING OFF PAGE CONNECTORS FOR ON PAGE CONNECTIONS
TOOLS>OPTIONS>VARIABLES
[56] VREGS: GFXCORE OUTPUT PHASE 3 & 4
[57] VREGS: CPUCORE OUTPUT PHASE
[59] VREGS: MEMPHY OUTPUT
[58] VREGS: MEMIO & MEMPHY
[5] SOC: POWER: V_GFXCORE
[24] MEMORY: CHANNEL C
Cactus 1/82 1/82 G-R 0.
Thu Apr 20 16:18:47 2017
DRAWING
D
B
C
A
B
D
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
PAGE
2.SEE PAGES 77 AND 79 FOR ADDITIONAL PCIE SPARE LANE INFORMATION
1.TO SUPPORT PCIE SPARE LANE INTERFACE (J28), POPULATE C215 AND C
NOTES:
SOC:PCIEX,CLOCKS
Cactus 2/82 2/82 G-R 0.
SOC_BASE
IC
X950118-
1 OF 30
ANUBIS
BGA
402
0.1 UF10% X5R
V
0.1 UF10%
402
X5R
V
0.1 UF10%
402
X5R
V
0.1 UF10%
402
X5R
V
M2_ONLY 0.1 UF10%
402
X5R
V
M2_ONLY 0.1 UF10%
402
X5R
V
M2_ONLY 0.1 UF10%
402
X5R
V
M2_ONLY 0.1 UF10%
402
X5R
V
0.1 UF 10%
402
V
EMPTY
402
X5R
V
0.1 UF10%
0.1 UF
V
402
EMPTY
10%
0.1 UF10%
V
X5R 402
M2_ONLY 0.1 UF10%
402
X5R
V
M2_ONLY 0.1 UF10%
402
X5R
V
M2_ONLY 0.1 UF10%
402
X5R
V
10%
402
M2_ONLY
X5R
V
0.1 UF
V_SOCPHY
402
200 OHM 1% CH
402
CH
1%
200 OHM
V_SOCPHY
402
510 OHM 5% CH
CH
5%
402
510 OHM
I106 X950118-001^ EMPTY^ U1 PROCSR-CPU-GPU,SM,1.0GHZ,BGA2049,ANUBIS^ SOC_EMPTY
X950118-001 (^) IC U I105 PROCSR-CPU-GPU,SM,1.0GHZ,BGA2049,ANUBIS^ SOC_INCLUDE
ANUBIS
IC
X950118-
2 OF 30
BGA
ZZ
ZZ
U1 U1 U
U
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
R VDD_BURN
R
R
R
35
35
35
35
7739
42
42
39
76
76
76
76
76
39 76
76
76
39 39 7739
35
42 42
7739
35
35 35
76 76 76
76
76
76
76
76
79
79
79
79
7739
2
2
2
2
BYPASSCLK_P
PEX_SOC_ENET_TN PEX_L1_SOC_SB_TP
PEX_SOC_SPARE_TN_C
PEX_SOC_SPARE_TP_C
PEX_SOC_ENET_TP_C
PEX_L1_SOC_SB_TP_C
PEX_L1_SOC_SB_TN_C
PEX_L3_SOC_M2_TP_C
PEX_SPARE_SOC_TN
PEX_SPARE_SOC_TP
PEX_ENET_SOC_TP_C PEX_ENET_SOC_TN_C (^) P_ZVDD_
PEX_SOC_ENET_TN_C
PEX_SOC_ENET_TP
PEX_L1_SOC_SB_TN
PEX_L3_SOC_M2_TP PEX_L0_SOC_SB_TN
PEX_L2_SOC_M2_TN
PEX_L1_SB_SOC_TP_C PEX_L1_SB_SOC_TN_C
PEX_L0_SB_SOC_TP_C PEX_L0_SB_SOC_TN_C
PEX_L3_M2_SOC_TP PEX_L3_M2_SOC_TN PEX_L2_M2_SOC_TP
BYPASSCLK_N
SOC_AV_NS_100M_CLKN
SOC_NB_PEX_SS_100M_CLKN
SOC_SYNC_NS_100M_CLKP
SOC_AV_NS_100M_CLKP
BYPASSCLK_P
SOC_PEX_SS_100M_CLKN
SOC_PEX_SS_100M_CLKP
SOC_NB_PEX_SS_100M_CLKP
PEX_L1_SOC_M2_TN
PEX_SOC_SPARE_TN
PEX_SOC_SPARE_TP
PEX_L0_SOC_M2_TN_C
PEX_L2_SOC_M2_TN_C
PEX_L1_SOC_M2_TN_C
PEX_L1_SOC_M2_TP_C
PEX_L2_SOC_M2_TP_C
PEX_L0_SOC_M2_TP_C
P_ZVSS_
PEX_L3_SOC_M2_TN_C
PEX_L0_SOC_SB_TN_C
PEX_L0_SOC_SB_TP_C
SOC_SYNC_NS_100M_CLKN
PEX_L0_SOC_SB_TP
PEX_L3_SOC_M2_TN PEX_L2_SOC_M2_TP
PEX_L1_SOC_M2_TP
PEX_L2_M2_SOC_TN PEX_L1_M2_SOC_TP
PEX_L0_M2_SOC_TP
PEX_L1_M2_SOC_TN
PEX_L0_M2_SOC_TN PEX_L0_SOC_M2_TN
PEX_L0_SOC_M2_TP
BYPASSCLK_N
BJ BJ
BH
BK BK
BH BM BM
BG BG
BP
BN
BV BW BV BW BK BK BG BG
BU BV BU BV BL BL BH BH
BG BG BH BH BK BK BN BN
BE BE BG BG BK BK BL BL
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
2
1
2
1
2
1
PCIE
P_ZCAL_VSS
P_GPP_TX0_N
P_GPP_TX0_P
P_GPP_TX1_N
P_GPP_TX1_P
P_GPP_TX2_N
P_GPP_TX2_P
P_GPP_TX3_N
P_GPP_TX3_P
P_UMI_TX0_N
P_UMI_TX0_P
P_UMI_TX1_N
P_UMI_TX1_P
P_UMI_TX2_N
P_UMI_TX2_P
P_UMI_TX3_N
P_UMI_TX3_P
P_ZCAL_VDD_
P_GPP_RX0_N
P_GPP_RX0_P
P_GPP_RX1_N
P_GPP_RX1_P
P_GPP_RX2_N
P_GPP_RX2_P
P_GPP_RX3_N
P_GPP_RX3_P
P_UMI_RX0_N
P_UMI_RX0_P
P_UMI_RX1_N
P_UMI_RX1_P
P_UMI_RX2_N
P_UMI_RX2_P
P_UMI_RX3_N
P_UMI_RX3_P
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
CLOCKS
BYPASSCLK_N
BYPASSCLK_P
CLKIN_N
CLKIN_P
AV_CLKIN_N
AV_CLKIN_P
DISP_CLKIN_N
DISP_CLKIN_P
CLKIN_NB_N
IN CLKIN_NB_P
MS_PART# MATL REF_DES DESCR. BOM PROPERTY
D
B
C
A
B
D
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
PAGE
SOC: POWER: MEMIO,MEMPHY,CPUCORE,NBCORE,MISC
NOTE: X6S/X7R CAPACITORS USED NEAR SOC
V_MEMIO V_MEMIO
ANUBIS
1 UF
402
X6S
6.3 V
10%
V_FUSE
X6S 603
4.7 UF 10%
1 UF
402
X6S
6.3 V
10%
1 UF
402
X6S
10% 6.3 V
1 UF
402
X6S
6.3 V
10%
1 UF
402
X6S
6.3 V
10%
V_BAT
V_SOCPHY
V_MEMPHY
402
X6S
6.3 V
10%
1 UF
X6S 603
4.7 UF 10% 6.3 V
1 UF
402
X6S
6.3 V
10%
V_SOC1P8VDD
2
1
2
1
1 2
2
1
2
1
2
1
2
VDDBT_RTC_G
D
B
C
A
B
D
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
V_GFXCORE
D
B
C
A
B
D
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
ANUBIS
ANUBIS
D
B
C A
B
D C A
VER
CONFIDENTIAL MICROSOFT
PROJECT NAME PAGE CSA FAB
- Cactus 4/82 4/82 G-R 0. DUE TO HIGHER TEMPERATURES IN AREA - V_SOC1P - X950118- - BGA ANUBIS - 17 OF IC - BGA V_CPUCORE V_CPUCORE - 20 OF - X950118- IC - 1.3 A120 OHM0.09DCR FB 6.3 V - V_3P V_MEMPHY - 18 OF V_NBCORE - X950118- ANUBIS - BGA IC - X950118-001 BGA IC - 19 OF - U ANUBIS - U - U - C - C - FB - C - C972 C - C - C983 C - C - U - R VDD_BURN - R - R - R - R - R - R - R - R - R - R - T - T - T - T - T - T - T - T - T - T - T - T - T - V - V - V - V - Y - Y - Y - Y - AC - AC - AC - AC - AE - AE - AE - AE - AH - AH - AH - AH - AK - AK - AK - AK - AM - AM - AM - AM - AR - AR - AU - AU - B - B - C - C - D - D - D - D - D - D - E - E - E - E - E - E - E - E - F - F - F - F - F - H - H - H - H - H - H - J - J - J - K - K - K - K - K - K - L - L - M - M - N - N - R - AA - R - R - R - R - R - R
- AA
- T
- Y
- V
- V
- W
- W
- AC
- AC
- AD
- AD
- AD
- AD
- AJ
- AJ
- AJ
- AJ
- AK
- AY
- AL
- AW
- AP
- AP
- AT
- AT
- AU
- AW
- BB
- BB
- BB
- BB
- BD
- BD
- BD
- BD - V - V - V - V - V - V - V - V - V - V - V - W - W - W - W - W - W - W - W - W - W - Y - Y - Y - Y - Y - Y - Y - Y - Y - Y - Y - AA - AA - AA - AA - AA - AA - AA - AA - AA - AA - AC - AC - AC - AC - AC - AC - AC - AC - AC - AC - AC - AD - AD - AE - AE - AF - AF - AH - AH - AJ - AJ - AK - AK - AL - AL - AM - AM - AP - AP - AR - AR - AR - AT - AT - AT - AU - AU - AW - AW - AY - AY - BA - BA - BB - BB - BD - BD - BE - BE - BG - BG - BH - BH - BJ - BJ - BK - BK - BL - BL - BM - BM - BN - BN - BP - BP - BR - BR - BT - BT - BU - BU - BU - BU - BV - BV - BV - BW - BW - BW - BL - BB - BD - BD - BE - BE - BG - BG - BH - BH - BK - BK - BL - BL - BL - BM - BN - BP - BP - BR - BR - BT - BT - BU - BU - BU - BU - BV - BV - BV - BW - BW - BW - BN - BP - BR - BP - BR - BR - BT - BU - BV - BV - BV - BW - BP - BP - BR - BR - BT - BU - BB - BD - BD - BD - BD - BD - BT - BU - BV - VDD_MEM_ VDD MEM - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_MEM_ - VDD_CORE_ VDD CORE - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_CORE_ - VDD_MEMP_ VDD MEMP - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_MEMP_ - VDD_NB_ SPARES/POWER - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_NB_ - VDD_095_ VDD_FUSE - VDD_095_ - VDD_095_ - VDD_095_ - VDD_BURN_ - VDD_BURN_ - VDD_18_ - VDD_18_ - VDD_18_ - VDD_18_ - VDD_18_ - VDD_18_ - VDD_33_ - VDD_33_ - VDD_33_ - VDD_33_ - VDD_33_ - SPARE_ - SPARE_ - SPARE_ - SPARE_ - SPARE_ - SPARE_ - SPARE_ - SPARE_ - SPARE_ - Cactus 5/82 5/82 G-R 0. SOC: POWER: GFXCORE - 23 OF V_GFXCORE - X950118- - BGA IC - 22 OF ANUBIS - X950118- - BGA IC - BGA ANUBIS ANUBIS
- X950118- IC - 21 OF - V_GFXCORE V_GFXCORE V_GFXCORE U V_GFXCORE
- U1 U - AD - AD - AD - AD - AD - AD - AD - AD - AE - AE - AE - AE - AE - AE - AE - AE - AE - AF - AF - AF - AF - AF - AF - AF - AF - AF - AH - AH - AH - AH - AH - AH - AH - AH - AJ - AJ - AJ - AJ - AJ - AJ - AJ - AJ - AK - AK - AK - AK - AK - AK - AK - AK - AK - AL - AL - AL - AL - AL - AL - AL - AL - AL - AM - AM - AM - AM - AM - AM - AM - AM - AP - AP - AP - AP - AP - AP - AP - AP - AR - AR - AR - AR - AR - AR - AR - AR - AR - AT - AT - AT - AT - AT - AT - AT - AT - AT - AU - AU - AU - AU - AU - AU - AU - AU - AU - AW - AW - AW - AW - AW - AW - AW - AW - AW - AY - AY - AY - AY - AY - AY - AY - AY - AY - AY - AY - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BD - BD - BD - BD - BD - BD - BD - BD - BD - BD - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BG - BG - BG - BG - BG - BG - BG - BG - BG - BH - BH - BH - BH - BH - BH - BH - BH - BH - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BK - BK - BK - BK - BK - BK - BK - BK - BK - BL - BL - BL - BL - BL - BL - BL - BL - BL - BM - BM - BM - BM - BM - BM - BM - BM - BM - BN - BN - BN - BN - BN - BN - BN - BN - BN - BP - BP - BP - BP - BP - BP - BP - BP - BP - BR - BR - BR - BR - BR - BR - BR - BR - BR - BT - BT - BT - BT - BT
- BT
- BT
- BT
- BT
- BU
- BU
- BU
- BU
- BU
- BU
- BU
- BU
- BU
- BU
- BU
- BU
- BU
- BU
- BU
- BU
- BU
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- BW - VDD_GFX_ VDD GFX - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD GFX VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ VDD GFX - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - VDD_GFX_ - Cactus 6/82 6/82 G-R 0. SOC: POWER: VSS - BGA ANUBIS - 24 OF - X950118- - 27 OF IC - X950118- - BGA IC - X950118-001 BGA ANUBIS - 26 OF IC - BGA ANUBIS - X950118- IC - 25 OF - U - U1 U1 U - BN - BP - BP - BP - BP - BP - BP - BP - BP - BP - BP - BP - BP - BP - BP - BP - BP - BP - BP - J - BR - BR - BR - BR - BR - BR - BR - BR - BR - BR - BR - BR - BR - BR - BR - BR - BR - BT - BT - BT - BT - BT - BT - BT - BT - BT - BT - BT - BT - BT - BT - BT - BT - BT - BT - BU - BU - BU - BU - BU - BU - BU - BU - BU
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- BW - AJ - AJ - AJ - AJ - AJ - AJ - AJ - AJ - AJ - AJ - AJ - AJ - AJ - AJ - AK - AK - AK - AK - AK - AK - AK - AK - AK - AK - AK - AK - AL - AL - AL - AL - AL - AL - AL - AL - AL - AL - AL - AL - AL - AL - AL - AL - AL - AL - AL - AL - AM - AM - AM - AM - AM - AM - AM - AM - AM - AM - AM - AN - AN - AN - AN - AN - AN - AN - AN - AN - AN - AP - AP - AP - AP - AP - AP - AP - AP - AP - AP - AP - AP - AP - AP - AP - AP - AP - AP - AP - AR - AR - AR - AR - AR - AR - AR - AR - AR - AR - AR - AR - AR - AR - AR - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AT - AU - AU - AU - AU - AU - AU - AU - AU - AU - AU - AU - AU - AU - AU - AU - AU - AU - AU - AU - AW - AW - AL - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AW - AL - AW - AW - AK - AY - AY - AY - AY - AY - AY - AY - AY - AY - AY - AY - AY - AY - AY - AY - AY - AK - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BA - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BB - BC - BC - BC - BC - BD - BD - BD - BD - BD - BD - BD - BD - BD - BD - BD - BD - BD - BD - BD - BD - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BE - BF - BF - BG - BG - BG - BG - BG - BG - BG - BG - BG - BG - BG - BG - BG - BG - BG - BG - BG - BG - BG - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BH - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BJ - BK - BK - BK - BK - BK - BK - BK - BK - BK - BK - BK - BK - BK - BK - BK - BK - BK - BK - BK - BL - BL - BL - BL - BL - BL - BL - BL - BL - BL - BL - BL - BL - BL - BL - BL - BL - BL - BL - BL - BM - BM - BM - BM - BM - BM - BM - BM - BM - BM - BM - BM - BM - BM - BM - BM - BM - BN - BN - BN - BN - BN - BN - BN - BN - BN - BN - BN - BN - BN - BN - BN - GROUND BN - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ GROUND - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - GROUND VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ GROUND - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - Cactus 7/82 7/82 G-R 0. SOC: POWER: VSS - X950118- - 30 OF IC - BGA ANUBIS - BGA - X950118- IC - 29 OF - BGA
- X950118- IC - 28 OF - U1 U
- U - A - A - A - A - A - A - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - B - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - C - D - D - D - D - D - D - E - E - E - E - E - E - E - E - E - E - E - E - F - F - F - F - F - F - F - F - F - F - F - F - F - F - G - G - G - G - G - G - G - G - G - G - H - H - H - H - H - H - H - J - J - J - J - J - J - J - J - J - J - J - J - J - J - J - J - J - K - K - L - L - L - L - L - L - L - L - L - L - L - L - M - M - M - M - M - M - M - M - M - M - M - M - M - M - M - M - M - N - N - N - N - N - N - N - N - N - N - R - R - R - R - R - R - R - R - R - R - R - R - R - R - T - T - T - T - T - T - T - T - T - T - T - T - T - T - U - U - U - U - V - V - V - V - V - V - V - V - V - V - V - V - W - W - W - W - W - W - W - W - W - W - W - W - W - W - W - W - W - T - Y - Y - Y - Y - Y - Y - Y - Y - Y - Y - Y - Y - Y - Y - T - AA - AA - R - AA - AA - AA - AA - AA - AA - AA - AA - AA - AA - AA - AA - AA - AA - AA - AA - AA - AA - AA - R - AA - AA - AC - AC - AC - AC - AC - AC - AC - AC - AC - AC - AC - AC - AC - AC - AC - AC - AC - AC - AD - AD - AD - AD - AD - AD - AD - AD - AD - AD - AD
- AD
- AD
- AD
- AD
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- AE
- AE
- AE
- AE
- AE
- AE
- AE
- AE
- AE
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- AH
- AH
- AH
- AH
- AH
- AH
- AH
- AH
- AH
- AH
- AH
- AJ
- AJ
- AJ
- AJ
- AJ - VSS_ GROUND - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ GROUND - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - GROUND VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_ - VSS_
MEMORY: PARTITION F1/F
Cactus 8/82 8/82 G-R 0.
6 OF 30
X950118-
X950118-
X950118-
X950118-
X950118-
X950118- IC
X950118- IC
X950118- IC
X950118- IC
X950118- IC
BGA
ANUBIS
5 OF 30
X950118-
IC
BGA
ANUBIS
120 OHM
CH
U
U
U
U
U
U
R
31
31
31
31
31
31
31
31
31
31
31
31
31
31
31 31 31 31
31
31 31
31
31
31
30
30
30 30
30
30
30
30
31
30
30
30
30
30
30
30
30 30
30
31
30 30
30
30
30
30 30
30
30
30
31
30
30
30
30
31
31
31
31 31 31
31
31
31 31 31 31
31
31
31
31
31 31
31
31
31
31
30
30 30
30
30
30
30
30
31
30 30
30
30
30 31
30
30
30
30
31
30
30
30
30
30
30
30
30
30
30
31
30
30
30
31
31
31
31
31
31
31
31
F_MEM_VREFDQ
F1_CLK0_N
F1_CLK0_P
F1_WE_N
F1_CS0_N
F1_RAS_N
F1_CAS_N
F1_CKE
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F_MEM_CAL
F_DRAM_RESET
F1_DDBI_
F1_DDBI_
F1_DDBI_
F1_DDBI_
F1_EDC_
F1_EDC_
F1_EDC_
F1_EDC_
F1_WCK1_N
F1_WCK1_P
F1_WCK0_N
F1_WCK0_P
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F0_CLK0_N
F0_CLK0_P
F0_WE_N
F0_CS0_N
F0_RAS_N
F0_CAS_N
F0_CKE
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_DDBI_
F0_DDBI_
F0_DDBI_
F0_DDBI_
F0_EDC_
F0_EDC_
F0_EDC_
F0_EDC_
F0_WCK1_N
F0_WCK1_P
F0_WCK0_N
F0_WCK0_P
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_ADBI_N
F1_ADBI_N
AJ
AK
AK
AN AN
AT
AL
AL
AN
AJ
AJ
AK AK AK AL
AM
AG
AK
AU
AP
AP
AP
AN
AM
AL AM AK
AF
AE
AF
AF
AH
AJ
AH
AH
AG AK
AJ
AL
AF
AL
AF
AN
AT
AP
AT
AP
AW
AW
AY
AY
AN
AG
AJ
AU
AG
AG AG
AP
AN
AP
AD
AC
AD
BB
AY AY
AL AL
AT
AW
AW AU AY
BB
AY AY AW AW
AU
BC
AT
AG
AT
AR
AT AT AV AW AV AV
BD
BD
BD
BD
BB
BA
BB
AY
AP
AP
AU
AP
AY AW AY AN
AJ
AK
AJ
AK
AF
AF
AD AD
AU
BB
AU
AG
BD
BB
BB
AT AU
AT
2
1
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MEM CHANNEL F
F0_CLK0_N
F0_CLK0_P
F0_WE_N
F0_CS0_N
F0_RAS_N
F0_CAS_N
F0_CKE
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_MA_A
F0_ADBI
F0_DDBI_
F0_DDBI_
F0_DDBI_
F0_DDBI_
F0_EDC_
F0_EDC_
F0_EDC_
F0_EDC_
F0_WCK1_N
F0_WCK1_P
F0_WCK0_N
F0_WCK0_P
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
F0_DQ
MEM CHANNEL F
F_MEM_VREFDQ
F1_CLK0_N
F1_CLK0_P
F1_WE_N
F1_CS0_N
F1_RAS_N
F1_CAS_N
F1_CKE
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F1_MA_A
F_MEM_CAL
F_DRAM_RESET
F1_ADBI
F1_DDBI_
F1_DDBI_
F1_DDBI_
F1_DDBI_
F1_EDC_
F1_EDC_
F1_EDC_
F1_EDC_
F1_WCK1_N
F1_WCK1_P
F1_WCK0_N
F1_WCK0_P
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
F1_DQ
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
D
B
C
A
B
D
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
PAGE
MEMORY: PARTITION D1/D
Cactus 10/82 10/82 G-R 0.
10 OF 30
X950118-
IC
BGA
ANUBIS
9 OF 30
IC
X950118-001 BGA
ANUBIS
120 OHM
CH
U
U
R
25
25
25 25 25 25 25 25
25
25
26
25 25 25
25
25
25
25
25
25
25
26
25
25
25
25
25 25
25
25
25 25
26 25
25
25 25 25 25
25
26
26 26
26
26
26
26
26
26
26
26
26
26
26
26
26
26
26 26
26 26 26 26 26 26
26
26
26
26
26 26 26 26 26 26 26
26
26 26 26 26
26
26
26
26
26
26
26
26
26 26 26 26 26
25
25 25
25
25
26
25 25
25
25 25
25 25 25 25
25
26
25 25
25
25
25
25
25
25 25 25
26
26 D_MEM_VREFDQ
D1_CLK0_N
D1_CLK0_P
D1_WE_N
D1_CS0_N
D1_RAS_N
D1_CAS_N
D1_CKE
D1_MA_A
D1_MA_A
D1_MA_A
D1_MA_A
D1_MA_A
D1_MA_A
D1_MA_A
D1_MA_A
D_MEM_CAL
D_DRAM_RESET
D1_DDBI_
D1_DDBI_
D1_DDBI_
D1_DDBI_
D1_EDC_
D1_EDC_
D1_EDC_
D1_EDC_
D1_WCK1_N
D1_WCK1_P
D1_WCK0_N
D1_WCK0_P
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_MA_A
D0_CLK0_N
D0_CLK0_P
D0_WE_N
D0_CS0_N
D0_RAS_N
D0_CAS_N
D0_CKE
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_DDBI_
D0_DDBI_
D0_DDBI_
D0_DDBI_
D0_EDC_
D0_EDC_
D0_EDC_
D0_EDC_
D0_WCK1_N
D0_WCK1_P
D0_WCK0_N
D0_WCK0_P
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_ADBI_N
D1_ADBI_N
AA
BA
BA
J
BJ
K
G
BG
E
A A
AC
C
C A
A
A
F
K
A C
B
D C C A A C A A
B
B
D A
AG
AG
H
F
G
F
D
H
G K
H
J G K J K K
BC
J
H
D
E
D
G
F
D
D
C
AE
AE
B
A
K
L
E
E
G D
H
G
F
D G D
D
B
M
K
C A A
B
B
C A A A C
B
D C C A
N
AN
AN
N
L
L
L
N N
M
N
M
N N
M
J
L
N
A
A
N
L
G
H
G
F
F
E
2
1
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MEM CHANNELD
D0_CLK0_N
D0_CLK0_P
D0_WE_N
D0_CS0_N
D0_RAS_N
D0_CAS_N
D0_CKE
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_MA_A
D0_ADBI
D0_DDBI_
D0_DDBI_
D0_DDBI_
D0_DDBI_
D0_EDC_
D0_EDC_
D0_EDC_
D0_EDC_
D0_WCK1_N
D0_WCK1_P
D0_WCK0_N
D0_WCK0_P
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
D0_DQ
MEM CHANNEL D
D_MEM_VREFDQ
D1_CLK0_N
D1_CLK0_P
D1_WE_N
D1_CS0_N
D1_RAS_N
D1_CAS_N
D1_CKE
D1_MA_A
D1_MA_A
D1_MA_A
D1_MA_A
D1_MA_A
D1_MA_A
D1_MA_A
D1_MA_A
D1_MA_A
D_MEM_CAL
D_DRAM_RESET
D1_ADBI
D1_DDBI_
D1_DDBI_
D1_DDBI_
D1_DDBI_
D1_EDC_
D1_EDC_
D1_EDC_
D1_EDC_
D1_WCK1_N
D1_WCK1_P
D1_WCK0_N
D1_WCK0_P
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
D1_DQ
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
D
B
C
A
B
D
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
PAGE
MEMORY: PARTITION C1/C
Cactus 11/82 11/82 G-R 0.
12 OF 30
IC
X950118-001 BGA
ANUBIS
11 OF 30
X950118-
IC
BGA
ANUBIS
120 OHM
CH
U
U
R
23 23
23
23
23 23 23 23 23 23
24
23
23
23 23 23
23
23
23 23
23
24
23 23 23 23
23 23
23
23
23 23
24 23
23
23 23
23
23
23
24
24
24
24
24
24 24 24
24
24
24
24 24 24
24
24
24
24 24
24 24
24
24
24 24
24
24 24 24 24 24 24
24
24
24 24
24
24
24
24
24
24
24
24 24 24
24
24
24
24
24
24 24 24
23 23
23
23
23
24
23
23
23 23
23
23 23
23 23 23
24
23
23
23 23
23
23
23
23
23
23
24
24 C_MEM_VREFDQ
C1_CLK0_N
C1_CLK0_P
C1_WE_N
C1_CS0_N
C1_RAS_N
C1_CAS_N
C1_CKE
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C_MEM_CAL
C_DRAM_RESET
C1_DDBI_
C1_DDBI_
C1_DDBI_
C1_DDBI_
C1_EDC_
C1_EDC_
C1_EDC_
C1_EDC_
C1_WCK1_N
C1_WCK1_P
C1_WCK0_N
C1_WCK0_P
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C0_CLK0_N
C0_CLK0_P
C0_WE_N
C0_CS0_N
C0_RAS_N
C0_CAS_N
C0_CKE
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_DDBI_
C0_DDBI_
C0_DDBI_
C0_DDBI_
C0_EDC_
C0_EDC_
C0_EDC_
C0_EDC_
C0_WCK1_N
C0_WCK1_P
C0_WCK0_N
C0_WCK0_P
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_ADBI_N
C1_ADBI_N
B
A
B
J K
G
B G
E
A A A C C A
A
A
F
K
A C B D A A C C A C B A B A C A H G
F
G D H
F
G J H K G K J K K
B
D
J
H
D
E
D
G
F
D
D
D
A
E
B A
K
L
E
E
G D H G F D G D
D
B
M
K
C A B A B A C A A C B D A A C C
L
N N M N
L
L N M N J M L N N N
A
A
N
L
E
H G
F F
E
2
1
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MEM CHANNEL C
C0_CLK0_N
C0_CLK0_P
C0_WE_N
C0_CS0_N
C0_RAS_N
C0_CAS_N
C0_CKE
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_MA_A
C0_ADBI
C0_DDBI_
C0_DDBI_
C0_DDBI_
C0_DDBI_
C0_EDC_
C0_EDC_
C0_EDC_
C0_EDC_
C0_WCK1_N
C0_WCK1_P
C0_WCK0_N
C0_WCK0_P
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
C0_DQ
MEM CHANNEL C
C_MEM_VREFDQ
C1_CLK0_N
C1_CLK0_P
C1_WE_N
C1_CS0_N
C1_RAS_N
C1_CAS_N
C1_CKE
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C1_MA_A
C_MEM_CAL
C_DRAM_RESET
C1_ADBI
C1_DDBI_
C1_DDBI_
C1_DDBI_
C1_DDBI_
C1_EDC_
C1_EDC_
C1_EDC_
C1_EDC_
C1_WCK1_N
C1_WCK1_P
C1_WCK0_N
C1_WCK0_P
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
C1_DQ
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
OUT
BI
D
B
C
A
B
D
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
PAGE
MEMORY: PARTITION A1/A
Cactus 13/82 13/82 G-R 0.
16 OF 30
X950118-
IC
BGA
ANUBIS
15 OF 30
X950118-
IC
BGA
ANUBIS
120 OHM
CH
U
U
R
18
18 18
18 18
18
18
18 18
18
19
18
18
18
18
18 18
18
18
18
18
19
18
18
18
18
18 18 18 18
18 18
19
18
18
18
18 18 18
19
18
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19
19 19
19
19
19
19
19
19
19 19
19
19 19
19 19
19
19
19
19
19 19
19
19 19
18
18 18 18
18
19
18
18
18
18
18
18
18
18 18
18
19
18
18
18
18 18
18
18
18
18 18
19
19
A1_CLK0_N
A1_CLK0_P
A1_WE_N
A1_CS0_N
A1_RAS_N
A1_CAS_N
A1_CKE
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A_MEM_CAL
A_DRAM_RESET
A1_DDBI_
A1_DDBI_
A1_DDBI_
A1_DDBI_
A1_EDC_
A1_EDC_
A1_EDC_
A1_EDC_
A1_WCK1_N
A1_WCK1_P
A1_WCK0_N
A1_WCK0_P
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A_MEM_VREFDQ
A0_CLK0_N
A0_CLK0_P
A0_WE_N
A0_CS0_N
A0_RAS_N
A0_CAS_N
A0_CKE
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_DDBI_
A0_DDBI_
A0_DDBI_
A0_DDBI_
A0_EDC_
A0_EDC_
A0_EDC_
A0_EDC_
A0_WCK1_N
A0_WCK1_P
A0_WCK0_N
A0_WCK0_P
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_ADBI_N
A1_ADBI_N
AD
AJ
AK
AK
AN
AN
AT
AL
AL AN
AJ
AJ
AK AK AK AL
AM
AG
AK
AU
AP
AP AP AN AM AK AM AL AF
AE
AF AF
AH
AH
AH
AJ
AK AL
AJ
AN AF AG AF AL
AW
AT AW AT
AY
AP AY AP
AN
AG
AJ
AU
AG
AG AG
AP AN
AP
AC
AD
BB
AY AY
AL AL
AT
AW AW AU AY BB AY AY AW AW
AU
BB
AU
AG
AT
AR
AT AT AV AV AV AW BD BD BD BD BB AY BB
BA
AW AP AU AP AY AP AY AN AJ AK AJ AK AF AF AD AD
AU
BC
AT
AG
BD
BB BB
AT AU
AT
2
1
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MEM CHANNEL A
A_MEM_VREFDQ
A0_CLK0_N
A0_CLK0_P
A0_WE_N
A0_CS0_N
A0_RAS_N
A0_CAS_N
A0_CKE
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_MA_A
A0_ADBI
A0_DDBI_
A0_DDBI_
A0_DDBI_
A0_DDBI_
A0_EDC_
A0_EDC_
A0_EDC_
A0_EDC_
A0_WCK1_N
A0_WCK1_P
A0_WCK0_N
A0_WCK0_P
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
A0_DQ
MEM CHANNEL A
A1_CLK0_N
A1_CLK0_P
A1_WE_N
A1_CS0_N
A1_RAS_N
A1_CAS_N
A1_CKE
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A_MEM_CAL
A_DRAM_RESET
A1_ADBI
A1_DDBI_
A1_DDBI_
A1_DDBI_
A1_DDBI_
A1_EDC_
A1_EDC_
A1_EDC_
A1_EDC_
A1_WCK1_N
A1_WCK1_P
A1_WCK0_N
A1_WCK0_P
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_DQ
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
D
B
C
A
B
D
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
PAGE
SOC:DEBUG,SB SIGNALS,V_BAT
SENSE CONNECTION FOR VRTB
FOR THE RELEVANT SOC VR, AND MUST BE MEASURED WITH A DIFFERENTIAL PROBE
C1220, C1221, C1222, AND C1223 ARE THE QUALIFICATION/MEASUREMENT TEST POINTS
DUE TO HIGHER TEMPERATURES IN AREA
NOTE: SINCE C1222 AND C1223 ARE NEAR SOC,
V_BAT
NOM.VOLTAGE: 1.8V
STUFF R388 IF SOC IS NOT STUFFED
3.0V BATTERY
INPUT
NETNAME TO STAY CONSISTENT WITH SCB
CHANGE THEM TO X6S/X7R IF EVER STUFFED
RETURN FROM SOC FOR MEMPHY. NOT CHANGING
NOTE: SOC_MEMIO_S_RTN IS ACTUALLY SENSE
C144, C155 VALUE SELECTED
TO CENTER XTAL FREQ
Cactus 14/82 14/82 G-R 0.
1% 243 OHM CH 402
1% 243 OHM CH 402
2.2 PF
EMPTY 402 50 V +/-0.1PF
V_BAT
V_1P8STBY
0 OHM
402
CH
5%
0 OHM 5% 402 EMPTY
1% EMPTY 402
221 KOHM
0.1 UF 10%
402
EMPTY
16 V
NCP
EMPTY
X899201-
EMPTY SC
SOT-
402
0.1 UF 10% 16 V EMPTY
V_3P3STBY
LARGE-TP
LARGE-TP
V_GFXCORE
V_CPUCORE
1 UF10% 6.3 V EMPTY 402
10%
402
EMPTY
6.3 V
1 UF
402
EMPTY
6.3 V
1 UF10%
402
EMPTY
6.3 V
1 UF10%
5% CH
0 OHM
402
0 OHM 5% CH 402
402
0 OHM 5% CH
ANUBIS
BGA
IC
4 OF 30
X950118-
DEBUG
1 KOHM
CH
402 CH
1 KOHM
DEBUG
CH
10 KOHM
402 EMPTY
20 MOHM 5%
CH
5% 402
0 OHM
2.2 PF
+/-0.1PF
50 V
402
EMPTY SM
EMPTY
32.768 KHZ
V_SOC1P
V_1P8STBY
47 PF
DEBUG
EMPTY
5% 50 V 402
DEBUG
402
5% 50 V EMPTY
47 PF
V_1P8STBY
DEBUG
1%
402
475 OHM
EMPTY
475 OHM 1%
402
EMPTY
DEBUG
10 KOHM 5%
402
EMPTY
FT
C155 FT
R
R
R
C
U77 Q
C
DB
DB
DB
DB
DB
C
C
C
C
R
R
R
U
DB
R524 R
FT
FT
R
R
R
C
Y
C
C
R
R
DB
R
R
54 R
54
54
54
54
64
14 54
14 54
61
14 54
14 58
14 58
14 58
14 54
75 75
75
58
75
36
36
75 7536 7536 7536 7536
7536
39
54 36 75
36
36
5414
14 54
5814
5814
14 58
5414
14 58
14 54
61
TMS
SOC_PWR_OK
DBRDY
SOC_RST_N
DBREQ_L
RTC_VREG_IN_D RTC_VREG_OUT RTC_VREG_IN
GPIO_POSTOUT_
GPIO_POSTOUT_
GPIO_POSTOUT_
ANATSTOUT_N
SB_SOC_DATA
BP_
BP_
VDD_CORE_PROBE
BP_
BP_
RTCCLK
ANATSTOUT_P
THERMDA
DIECRACKMON
THERMDC
SVT
ANALOGOUT
ANATSTIN_P ANATSTIN_N
SB_SOC_CLK
SOC_CPUCORE_S
SOC_GFXCORE_S_RTN
SOC_MEMIO_S
SOC_MEMPHY_S
SOC_MEMIO_S_RTN
SOC_GFXCORE_S
SOC_MEMIO_S_RTN
PLLTEST
X32K_X2_R
SOC_CPUCORE_S_RTN
TRST_L
TDO TDI TCK
GPIO_1P8_
VDD_GFX_PROBE VSS_GFX_PROBE
VSS_MEMP_PROBE
VDD_MEMP_PROBE
VSS_CORE_PROBE
TMON_CAL
TMON_CAL
SVC
GPIO_1P8_
GPIO_3P3_
GPIO_3P3_
GPIO_3P3_
GPIO_3P3_
GPIO_1P8_ GPIO_POSTOUT_ GPIO_POSTOUT_ GPIO_POSTOUT_
X32K_X
ATE_TSTCLK_EN
SOC_THERMTRIP_N
X32K_X
GPIO_1P8_
PLLTEST
SVD_R_SOC
SVD
SVC_R_SOC
SOC_MEMIO_S_RTN SOC_GFXCORE_S_RTN
SOC_SOCPHY_S
SOC_CPUCORE_S_RTN
SOC_CPUCORE_S
SOC_NBCORE_S_RTN
SOC_NBCORE_S
SOC_GFXCORE_S
SOC_MEMPHY_S
SOC_MEMIO_S
SIC
SID
SVT_R_SOC
SP_SMC_INT_N
1
1
2
1
2
1
1 2
2
1
2 3
4 1
3
2
1 1
1
1
1
1
1 2
1 2
1 2
1 2
2
(^21)
(^21)
1
BR
BR
BD
BN
BP
BP
BW
A
L
BV
BK48 BV
BN
BV
N
B
K
BW
BK47 BW
BP
BP
BJ BH
BH BH
BL
BL
BE
BE
BF
BG
BG
BM BR BN BM BN BJ
BJ BL
BN
BP
BF
BE
BF BE
BH
BH
BG
BG
BE
BE BE
BG BG
BE
BK
BF
BD BE BE BE BN BK
BT
BT
BT BR BT BR BP BT BT
1
1
1
2
1
1 2
1 2
2 1
2
1
2
1
2
1
2
1
(^21)
1
2 1
BI 2 1
IN
OUT
OUT
OUT
FTP
FTP
NC GND
VIN VOUT
OUT
BI
OUT
BI
JTAG/DEBUG
VSS_CORE_PROBE
VDD_CORE_PROBE
VSS_095_SENSE
RESET_N
VSS_CORE_SENSE
VDD_CORE_SENSE
VSS_NB_SENSE
VDD_NB_SENSE
TMON_CAL
VSS_MEMP_PROBE
VDD_MEMP_PROBE
VSS_GFX_PROBE
VDD_GFX_PROBE
PWROK
DBREQ_N
1P8V_GPIO
1P8V_GPIO
TCK
TDI
TDO
TMS
TRST_N
DBRDY
1P8V_GPIO
3P3V_GPIO 3P3V_GPIO 1P8V_GPIO 1P8V_GPIO 1P8V_GPIO 1P8V_GPIO 1P8V_GPIO 1P8V_GPIO 1P8V_GPIO
A0_BYPASS
THERMTRIP_N
X32K_X X32K_X
3P3V_GPIO 3P3V_GPIO
PSEN
DLY_PSP_RESET
ATE_TSTCLK_EN
VDD_095_SENSE
RTCCLK
SIC
SID
SVC
SVD
SVT
ALERT_N
BP_
BP_
BP_
THERMDC
THERMDA
BP_
DIECRACKMON
ANALOGOUT
ANATSTIN_P ANATSTIN_N
ANATSTOUT_P ANATSTOUT_N
PLLTEST
PLLTEST
TMON_CAL
VDD_MEM_SENSE VDD_MEMP_SENSE VSS_MEM_SENSE
VDD_GFX_SENSE
VSS_GFX_SENSE OUT
BI
BI
BI
OUT
OUT
OUT
FTP
FTP
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
BI
D
B
C
A
B
D
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
PAGE
15 0805 22UF EMPTY
4 0603 4.7 UF 10 0603 10UF
13 0805 22UF
5 0402 1UF
27 0805 22UF
12 0805 10UF
SOC: DECOUPLING
3 0402 1UF
22 0603 10UF
NOTE: X6S/X7R CAPACITORS USED NEAR SOC DUE TO HIGHER TEMPERATURES IN AREA
Cactus 16/82 16/82 G-R 0.
22 UF20% 6.3 V X6S 805
22 UF 20% 6.3 V EMPTY 805
20% 6.3 V EMPTY
22 UF
805
V_NBCORE
805
X6S
6.3 V
22 UF20%
805
EMPTY
20% 6.3 V
22 UF
6.3 V X6S 805
22 UF20%
805
22 UF20% 6.3 V EMPTY
22 UF EMPTY
6.3 V 805
20%
805
EMPTY
22 UF20% 6.3 V
V_NBCORE
4.7 UF 6.3 V
10% X6S 603
6.3 V
4.7 UF
603
X6S
10%
X6S
6.3 V
4.7 UF 10%
603
10% 6.3 V X6S 603
4.7 UF
10 UF 6.3 V X6S
20%
603
603
10 UF20% 6.3 V X6S
V_NBCORE
10 UF 6.3 V
20% X6S 603
X6S
20%
603
6.3 V
10 UF
603
20% X6S
6.3 V
10 UF
603
20% X6S
6.3 V
10 UF
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
20% X6S 603
6.3 V
10 UF
6.3 V
10 UF
603
20% X6S
V_NBCORE
805
X6S
6.3 V
22 UF 20%
22 UF20% 6.3 V X6S 805
20% X6S 805
6.3 V
22 UF
22 UF 20% 6.3 V 805
X6S
6.3 V
805
22 UF 20% EMPTY
805
X6S
6.3 V
22 UF 20%
805
6.3 V X6S
22 UF 20%
805
6.3 V
22 UF20% X6S
805
6.3 V X6S
22 UF 20%
22 UF 6.3 V X6S
20%
805
805
6.3 V X6S
22 UF20%
X6S
6.3 V
22 UF
805
20%
6.3 V
22 UF X6S
20%
805
6.3 V
22 UF X6S 805
20%
805
6.3 V
20% X6S
22 UF
20% X6S 805
22 UF 6.3 V
805
X6S
6.3 V
22 UF20%
20%
805
6.3 V
22 UF X6S
V_NBCORE
6.3 V
805
X6S
22 UF20%
10% 6.3 V X6S 402
1 UF
10% 6.3 V X6S 402
1 UF
X6S
6.3 V
1 UF10%
402
10% 6.3 V X6S 402
1 UF
6.3 V
1 UF
402
10% X6S
V_SOCPHY
10 UF20%
805
X6S
6.3 V
10 UF20%
805
X6S
6.3 V
10 UF20%
805
X6S
6.3 V
10 UF20%
805
X6S
6.3 V
10 UF20%
805
X6S
6.3 V
10 UF20%
805
X6S
6.3 V
10 UF20%
805
X6S
6.3 V
10 UF20%
805
X6S
6.3 V
10 UF20%
805
X6S
6.3 V
V_CPUCORE
10 UF20%
805
X6S
6.3 V
10 UF20%
805
X6S
6.3 V
6.3 V
10 UF20%
805
X6S
805
22 UF20% X6S
6.3 V
805
6.3 V
22 UF X6S
20%
805
6.3 V X6S
22 UF 20%
20% 6.3 V
22 UF X6S 805
X6S
22 UF20% 6.3 V 805
22 UF 20%
805
6.3 V X6S
805
6.3 V X6S
22 UF 20%
805
6.3 V X6S
22 UF 20%
805
6.3 V
20% X6S
22 UF
805
6.3 V X6S
22 UF 20%
805
6.3 V X6S
22 UF 20%
6.3 V X6S
22 UF20%
805
805
6.3 V X6S
22 UF 20%
805
6.3 V X6S
22 UF 20%
805
6.3 V X6S
22 UF 20%
805
6.3 V X6S
22 UF 20%
805
6.3 V X6S
22 UF20%
22 UF 6.3 V 805
X6S
20%
805
6.3 V X6S
22 UF 20%
805
X6S
22 UF 20% 6.3 V
805
6.3 V X6S
22 UF 20%
6.3 V
805
X6S
22 UF 20%
805
6.3 V X6S
22 UF 20%
805
X6S
22 UF 20% 6.3 V
X6S
22 UF 20% 6.3 V 805 805
6.3 V X6S
22 UF 20%
V_CPUCORE
6.3 V X6S
22 UF 20%
805
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
603
X6S
6.3 V
10 UF20%
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
6.3 V
10 UF20% X6S 603
10 UF 6.3 V 603
X6S
20%
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
10 UF 6.3 V X6S
20%
603
V_CPUCORE
6.3 V
20%
603
X6S
10 UF 10 UF 6.3 V X6S
20%
603
603
10 UF 6.3 V X6S
20%
10 UF 6.3 V X6S
20%
603
402
X6S
10% 6.3 V
1 UF
1 UF 6.3 V 402
10% X6S
402
X6S
1 UF10% 6.3 V
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C924 C
C
C
C
C
C
C
C
C884 C
C824 C921 C
C899 C
C867 C
C
C
C
C
C901 C
C
C
C
C
C877 C
C
C
C879 C
C
C
C
C
C
2 1
2 1
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2 1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2 1 2
1 2 1 2 1 2
1 2 1 2
1 2 1 2
1 2
1 2
1 2
1 2
1 2 1 2
1 2
1 2
1 2
1 2
1 2 1 2
1 2
1 2
1 2 1 2
1 2
1 2
1 2
1 2
1 2
D
B
C
A
BD
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
PAGE
SOC: DECOUPLING
68 0402 0.22UF 8 0603 10UF^8 0402 1UF 19 0603 10UF
NOTE: X6S/X7R CAPACITORS USED NEAR SOC DUE TO HIGHER TEMPERATURES IN AREA
Cactus 17/82 17/82 G-R 0.
0.22 UF10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF 10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
X6S
0.22 UF10%
402
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF 10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
10%
402
X6S
6.3 V
0.22 UF
0.22 UF10%
402
X6S
6.3 V
0.22 UF10% X6S
6.3 V 402
0.22 UF 10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF 10% X6S
6.3 V 402
0.22 UF10%
402
X6S
6.3 V
402
0.22 UF 10% X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
10% 6.3 V
0.22 UF
402
X6S
0.22 UF 10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF 10%
402
X6S
6.3 V
6.3 V
0.22 UF10%
402
X6S
V_MEMIO
6.3 V
0.22 UF 10%
402
X6S
0.22 UF 6.3 V X6S
10%
402
X6S 402
0.22 UF 10% 6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF 10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF 10% 6.3 V 402
X6S
0.22 UF 6.3 V
10%
402
X6S
0.22 UF 10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF 10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF10% X6S
6.3 V 402
0.22 UF10% X6S
6.3 V 402
0.22 UF
402
X6S
6.3 V
10%
0.22 UF10%
402
X6S
6.3 V
10%
402
X6S
6.3 V
0.22 UF
X6S
0.22 UF10%
402
6.3 V
0.22 UF 6.3 V 402
X6S
10%
0.22 UF 10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF 10%
402
X6S
6.3 V
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF 10%
402
X6S
0.22 UF
402
X6S
6.3 V
10%
6.3 V
0.22 UF 10%
402
X6S
402
0.22 UF 10% X6S
6.3 V
402
0.22 UF10% X6S
6.3 V
6.3 V
0.22 UF 10%
402
X6S
0.22 UF
402
X6S
6.3 V
10%
0.22 UF10%
402
X6S
6.3 V
X6S
6.3 V
0.22 UF10%
402
0.22 UF10%
402
X6S
6.3 V
0.22 UF 6.3 V 402
10% X6S
10% 6.3 V
0.22 UF
402
X6S
0.22 UF10%
402
X6S
6.3 V
402
10% X6S
6.3 V
0.22 UF
20%
603
X6S
10 UF 6.3 V
6.3 V
20%
603
X6S
10 UF
6.3 V
10 UF20%
603
X6S
603
X6S
20% 6.3 V
10 UF
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF20%
603
X6S
603
6.3 V
10 UF20% X6S
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF20%
603
X6S
10 UF 20% 6.3 V 603
X6S
10 UF 6.3 V
20%
603
X6S
10 UF 6.3 V
20%
603
X6S
V_MEMPHY
6.3 V
20%
603
X6S
10 UF
402
1 UF X6S
10% 6.3 V
1 UF10% 6.3 V X6S 402
1 UF10% 6.3 V X6S 402
402
1 UF X6S
10% 6.3 V
402
X6S
1 UF 6.3 V
10%
402
X6S
6.3 V
1 UF 10%
V_MEMIO
6.3 V
1 UF10% X6S 402
1 UF10% 6.3 V X6S 402
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF20%
603
X6S
6.3 V
10 UF 20%
603
X6S
20% 6.3 V
10 UF
603
X6S
6.3 V
10 UF20%
603
X6S
10 UF
603
X6S
6.3 V
20%
V_MEMIO
0.22 UF10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
0.22 UF10% 6.3 V X6S 402
0.22 UF10%
402
X6S
6.3 V
0.22 UF10%
402
X6S
6.3 V
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C655 C
C646 C661 C890 C905 C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2 1 2
1 2 1 2 1 2 1 2 1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
1 2
D
B
C
A
BD
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
PAGE
MEMORY: CHANNEL A
PINS A4-M2 USE LEFT SIDE VALUES
MIRROR FUNCTION DISABLED WITH PIN J1 LOW
Cactus 19/82 19/82 G-R 0.
DDR5_8GBX
1 OF 2
IC
M1005505-001 BGA
DDR5_8GBx
2 OF 2
IC
M1005505-001 BGA
GDDR5_BASE
CH
5.49 KOHM
2.37 KOHM
CH
V_MEMIO
1 UF 10% 6.3 V X5R 402
CH
60.4 OHM
V_MEMIO
CH
60.4 OHM
120 OHM
CH
V_MEMIO
R
R
C
R425 R
R
U
U
13
13
13
13
13
13 13
13
13
13 13
13 13
13
13
13
19
1913
1913
19
18
13
13
13
13 13
13
1913
1913
13
13
13
13
13
13 13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13 13
13
13
13
13
13
13
13
13 13
13
13
13
13 13
A1_VREFC
A1_DQ
A1_DQ A1_DQ
A1_DQ
A1_DQ
A1_DQ A1_DQ A1_DQ
A1_DQ
A1_DQ A1_DQ A1_DQ A1_DQ A1_DQ A1_DQ
A1_DQ
A1_DQ
A1_DQ A1_DQ A1_DQ A1_DQ A1_DQ A1_DQ
A1_DQ
A1_DQ
A1_DQ
A1_MA_A
A1_MA_A
A1_WCK1_N
A1_WCK1_P
A1_CKE
A1_CLK0_N
A1_CLK0_P
A1_RAS_N
A1_DDBI_
A1_DDBI_
A1_EDC_
A1_EDC_
A1_WCK0_N
A1_WCK0_P
A1_EDC_
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_MA_A
A1_DQ A1_DQ A1_DQ
A1_DQ
A1_DQ
A1_DDBI_
A1_DDBI_
A1_CLK0_N
A1_CLK0_P
A1_VREFC
A1_EDC_3 A1_DQ
A1_ADBI_N
A1_ZQ
A1_CS0_N
A1_WE_N
A1_CAS_N
A_DRAM_RESET_R
2
1
2
1
2
1
2
1
2
1
J
L
P P
D D
J
J
G
U
A
J
R R C C
M
M
N
N
T
T
U
U
M
M
N
N
T
T
U
U
F
F
E
E
BB
AA
F
F
E
E
B
B
A
A
P P D D
G
J
J J
L
H K K H
J
J K H H K
U
R
N
E
C
AK
H
U
R
N
E
C
A
R
C
M
F
M
F
R
C
U
R
N
E
C
A
K
H
U
R
N
E
C
A
K
H
T
P
L
G
D
BT
L
G
BK
H
U
A
J
T
P
M
F
D
BL
G
T
P
M
K
H
F
D
BN
E
N
E
T
P
M
K
H
F
D
B
L
G
T
P
M
F
D
B
L
G
P
L
G
D
R
C
R
C
L
G
L
G
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MF=0/MF=
ZQ
WE_N/CS_N
WCK23_N/WCK01_N
WCK23_P/WCK01_P
WCK01_N/WCK23_N
WCK01_P/WCK23_P
SEN
RESET_N
RAS_N/CAS_N
NC_
NC_
MF0/MF
EDC3/EDC EDC2/EDC EDC1/EDC EDC0/EDC
DQ31/DQ
DQ30/DQ
DQ29/DQ
DQ28/DQ
DQ27/DQ
DQ26/DQ
DQ25/DQ
DQ24/DQ
DQ23/DQ
DQ22/DQ
DQ21/DQ
DQ20/DQ
DQ19/DQ
DQ18/DQ
DQ17/DQ
DQ16/DQ
DQ15/DQ
DQ14/DQ
DQ13/DQ
DQ12/DQ
DQ11/DQ
DQ10/DQ
DQ9/DQ
DQ8/DQ
DQ7/DQ
DQ6/DQ
DQ5/DQ
DQ4/DQ
DQ3/DQ
DQ2/DQ
DQ1/DQ
DQ0/DQ
DBI3_N/DBI0_N DBI2_N/DBI1_N DBI1_N/DBI2_N DBI0_N/DBI3_N
CS_N/WE_N
CKE_N
CK_N
CK_P
CAS_N/RAS_N
BA3_A3/BA1_A BA2_A4/BA0_A BA1_A5/BA3_A BA0_A2/BA2_A
ABI_N
A9_A1/A11_A A8_A7/A10_A
A12_A A11_A6/A9_A A10_A0/A8_A
BI
POWER/GROUND
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VREFD_
VREFD_
VREFC_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
D
B
C
A
BD
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
PAGE
MEMORY: CHANNEL B
MIRROR FUNCTION ENABLED WITH PIN J1 HIGH PINS A4-M2 USE RIGHT SIDE VALUES
Cactus 20/82 20/82 G-R 0.
DDR5_8GBX
1 OF 2
IC
M1005505-001 BGA
49.9 OHM 1%
402 CH
10 OHM
CH
NPO
120 PF 50 V 402
5%
4.99 KOHM
CH
V_MEMIO
IC
M1005505-001 BGA
2 OF 2
DDR5_8GBx
GDDR5_BASE
5.49 KOHM
CH
2.37 KOHM
CH
V_MEMIO
CH
60.4 OHM
1 UF 10% X5R 402
6.3 V
60.4 OHM
CH
V_MEMIO
CH
120 OHM
V_MEMIO
R
R
R
C
R
R
U
R448 R
R
C
U
12
12
12
12
12
12
12
12
12
12
12
12 20 21
2012
2012
20
12
2120
12
12
12
12
12
2012
2012
12
12
12
12
12
12 12
12
12
12
12
12
12
12
12
12
12
12 12
12
12
12 12 12
12
12
12
12
12
12
12 12
12
12
12
12
12
12
12 12
12
12
20 B0_VREFC
B_DRAM_RESET B_DRAM_RESET_R
B0_DQ
B0_DQ
B0_DQ B0_DQ B0_DQ
B0_DQ
B0_DQ
B0_DQ
B0_DQ
B0_DQ B0_DQ
B0_DQ
B0_DQ
B0_DQ
B0_DQ
B0_DQ
B0_DQ
B0_DQ
B0_DQ
B0_DQ B0_DQ
B0_DQ
B0_DQ
B0_DQ
B0_DQ
B0_WCK1_N
B0_EDC_
B0_MA_A
B0_MA_A
B0_MA_A
B0_DDBI_ B0_DDBI_ B0_DDBI_
B0_WCK0_P
B0_WCK1_P
B0_DDBI_
B0_CLK0_N
B0_CKE
B0_CLK0_P
B0_WE_N
B0_RAS_N
B0_CS0_N
B0_CAS_N
B0_ZQ
B0_WCK0_N
B0_EDC_
B0_MA_A
B0_MA_A B0_MA_A B0_MA_A
B0_DQ
B0_DQ
B0_CLK0_P
B0_VREFC
B0_EDC_
B0_EDC_
B0_DQ B0_DQ
B0_DQ B0_DQ B0_DQ
B0_MA_A
B0_MA_A
B0_ADBI_N
B0_CLK0_N
B_DRAM_RESET_C
B_DRAM_RESET_R
2
1
2
1
2
1
2
1
2
1
2
1
J
L
P P
D D
J
J
G
U
A
J
R R C C
M
M
N
N
T
T
U
U
M
M
N
N
T
T
U
U
F
F
E
E
B
BB
A
A
F
F
E
E
B
B
A
A
P P D D
G
J
J J
L
H
K K H
J
J K H H K
1 2 1 2
2
1
2
1
U
R
N
E
C
A
K
H
U
R
N
E
C
A
R
C
M
F
M
F
R
C
U
R
N
E
C
A
K
H
U
R
N
E
C
A
K
H
T
P
L
G
D
BT
L
G
BK
H
U
A
J
T
P
M
F
D
BL
G
T
P
M
K
H
F
D
BN
E
N
E
T
P
M
K
H
F
D
B
L
G
T
P
M
F
D
B
L
G
P
L
G
D
R
C
R
C
L
G
L
G
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
MF=0/MF=
ZQ
WE_N/CS_N
WCK23_N/WCK01_N
WCK23_P/WCK01_P
WCK01_N/WCK23_N
WCK01_P/WCK23_P
SEN
RESET_N
RAS_N/CAS_N
NC_
NC_
MF0/MF
EDC3/EDC EDC2/EDC EDC1/EDC EDC0/EDC
DQ31/DQ
DQ30/DQ
DQ29/DQ
DQ28/DQ
DQ27/DQ
DQ26/DQ
DQ25/DQ
DQ24/DQ
DQ23/DQ
DQ22/DQ
DQ21/DQ
DQ20/DQ
DQ19/DQ
DQ18/DQ
DQ17/DQ
DQ16/DQ
DQ15/DQ
DQ14/DQ
DQ13/DQ
DQ12/DQ
DQ11/DQ
DQ10/DQ
DQ9/DQ
DQ8/DQ
DQ7/DQ
DQ6/DQ
DQ5/DQ
DQ4/DQ
DQ3/DQ
DQ2/DQ
DQ1/DQ
DQ0/DQ
DBI3_N/DBI0_N DBI2_N/DBI1_N DBI1_N/DBI2_N DBI0_N/DBI3_N
CS_N/WE_N
CKE_N
CK_N
CK_P
CAS_N/RAS_N
BA3_A3/BA1_A BA2_A4/BA0_A BA1_A5/BA3_A BA0_A2/BA2_A
ABI_N
A9_A1/A11_A A8_A7/A10_A
A12_A A11_A6/A9_A A10_A0/A8_A
IN OUT
POWER/GROUND
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSSQ_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VSS_
VREFD_
VREFD_
VREFC_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDDQ_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
VDD_
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
D
B
C
A
B
D
C
A
VER
CONFIDENTIAL
MICROSOFT
PROJECT NAME PAGE CSA FAB
PAGE
