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Ryerson Polytechnic University Department of Electrical and Computer Engineering ELE 328 – Digital Systems and Microprocessors
Lab 1 CAD Tools 10 marks (2 Weeks) Fall 2002 Due Date: Week 4
Part A – PALASM “Tutorial Introduction”
A.1 Objectives:
- The main objective of this lab is to know how to use PALASM software. PALASM is used for Synthesis of digital logic design using PALs (programmable devices which can replace conven- tional logic circuits).
A.2 Installing Your Own Copy of PALASM for Home Use – Done later
- System Requirements o IBM PC/XT using DOS version 3.0 or later o 1.44 MB/3.5 in. floppy drive for software installation o Available memory for PALASM > 512 KB o Available Hard disk space > 10 MB
- License: Advance Micro Devices (AMD) has authorized PALASM software for unrestricted stu- dent use. The software is available to the student on the network in system directory /pub/DOS/palasm
- PALASM Files o On the network, cd /pab/DOS/palasm o Floppy disk No.1 in drive “A” cd /disk mcopy * a: o Floppy disk No.2 in drive “A” cd /disk mcopy * a: o Floppy disk No.3 in drive “A” cd /disk mcopy * a: o Optional disk Floppy disk No.4 in drive “A” cd /disk mcopy * a:
- Installation o Place installation disk 1 into drive “A”. o Type “install” and [enter]. The AMD copyright screen appears. Press any key. o Proceed with the installation
A.3 Procedure – Preparing the Program File
A suitable PAL programming file must be created before we can proceed with the compilation, simula- tion, and ultimately, the actual device programming processes. For this project #1 Part A, we prefer to use “lab1.pds” for the name of such a file (created in Lab 0 from page 7 lab1). Any editor program may be used to prepare the file. If you use a word processing program, be sure to create the file in such a way that the file contains no special formatting characters. In some word processors (e.g. WordStar), use the non-document mode. In others, it is saved ASCII or print to disk to create the file. After the file has been created, it is a good idea to use the DOS TYPE command to examine the file. It should contain only printable characters. Note on VIRUSES: Almost all students’ disks are contaminated with viruses. A virus on your disk will eventually corrupt program and/or data files. Use the ALERT.EXE program to check your disk and remove viruses. Instructions are contained in the document file (*.doc). We use the JOVE editor from any workstation^1 to prepare the required file. The file should be edited according to the following format:
- Edit the TITLE, PATTERN, REVISION, AUTHOR, COMPANY and DATE.
- Select the PAL configuration for CHIP. We are using PAL16V8, to be proceeded by the label lab
- Assign the 20 pins of the PAL to the input and the output signals like A,B,C,D,… and F1,F2,… Assign pin#10 to GND, and pin#20 for VCC. Use NC (no connection) for pins with no connec- tion
- Write the logic Equations for the output signals as a function of input signals like F1=ABC + /AB/C +…
- Write test vectors for SIMULATION. This is important to test the function for given inputs. Use " TRACE-ON " to set the probes on some (or all) input and output signals that we want to test. Set signal values by using "SETF". For example, SETF /A B /C D /E means to test the value of F1 when A=0, B=1, C=0, D=1 and E=0. We would simulate every input condition like the truth table. Use " TRACE-OFF " to end the simulation.
- Store^2 labl.pds file on a 3.5-inch floppy disk.
A.4 Procedure – Compiling and Simulation
To compile and simulate labl.pds at the PAL station, we do the following sequence of steps:
- Insert your floppy disk (with the labl.pds file) into drive A: of the PAL station.
- Type palasm , hit < cr > key, then press any key to start the PAL session.
- Change the directory to A: from the file menu.
- Type r to retrieve existing design. Hit < cursor-down > once, then press < cr > to list the *.pds files from the A: drive.
- Move cursor down to highlight labl.pds, and then hit < cr > to make the choice.
- Press < F10 > key to accept the file selection.
- Move cursor right to open the RUN menu, and type b to select BOTH. Make sure the log file name is lab1.log. (If not, type it in.)
- Press < F10 > key twice to proceed to the compilation and simulation. This process would last a minute or two. If all goes well, there should be a zero count of error (or warning).
(^1) It is possible to create this file directly from the PAL station. (^2) Done in lab 0.
A.6 An Example of the PALASM File
TITLE A VOTING MACHINE USING PALS PATTERN LAB1.PDS REVISION A AUTHOR YOUR NAME COMPANY RYERSON DATE MM/DD/
CHIP lab1 PAL16V8 ; USE "VERSATILE" TYPE PLD.
NC A B C D NC NC NC NC GND NC NC TIE NO YES NC NC NC NC VCC
;The following illustrates a few basic principles in writing a PALASM program. ;Design a PAL circuit that will display the results of a vote among 4 persons A, B, C and D. ;INPUTS: [ABCD] yes = 1 ; no = 0 ;OUTPUTS: YES ("yes" majority) = 1 ; NO ("no" majority) = 1 ; TIE (tie vote) = 1
Equations
YES = /ABCD + A/BCD + AB/CD + ABC/D + ABCD NO = /A/B/C/D + /A/B/CD + /A/BC/D + /AB/C/D + A/B/C/D TIE = /A/BCD + /AB/CD + /ABC/D + A/B/CD + A/BC/D + AB/C/D
SIMULATION
TRACE_ON A B C D YES NO TIE ;Determines signals to be displayed and their order. SETF /A /B /C /D ;Default (TRACE-ON not used), as on pins. SETF D SETF C /D SETF D SETF B /C /D SETF D SETF C /D SETF D SETF A /B /C /D SETF D SETF C /D SETF D SETF B /C /D SETF D SETF C /D SETF D TRACE_OFF
A.7 An Introduction to PALASM
The following describes a relatively simple project to illustrate a few basic principles in writing a PA- LASM program.
A.7.1 Design Project
Design a PAL circuit that will display the results of a vote among four persons [ABCD]. A “sum-of-products” solution is derived from the truth table and implemented with a PAL device.
INPUTS: [ ABCD ] yes = 1 no = 0
OUTPUTS: YES = 1 (“yes” majority) NO = 1 (“no” majority) TIE = 1 (tie vote)
A.7.2 PAL Device CONNECTION DIAGRAM Top View
- The PAL device used is the LATTICE GAL16V8A, or the equivalent AMD device, PALCE16V8.
- In the simple mode (combinational) used in the design file "VOTE.pds" no memory or register is used.
- In the simple mode, pins 15 & 16 do not have a feedback capabil- ity, and must always be configured as dedicated outputs.
- In the registered mode (RVOTE.pds) pin 1 & pin 11 are perma- nently configured as clock and output enable.
Note: Pin 1 is marked for orientation
PIN DESIGNATORS
CLK - Clock I/O - Input/Output GND - Ground OE - Output Enable I - Input VCC - Supply Voltage
A B C D YES NO TIE
PAL
A
B
C
D
YES
NO
TIE
1 2 3 4 5 6 7 8 9
10
18
20 19
17 16 15 14 13 12 11
CLK/I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 I 8 GND
VCC I/O 7 I/O 6 I/O 5 I/O 4 I/O 3 I/O 2 I/O 1 I/O 0 OE/I 9
A.7.5 Registered Mode
- The design file RVOTE.pds causes the software to select the “registered” mode of operation. The change to output signals due to input signal variations are not available until a clock pulse is applied.
TITLE PAL VOTING MACHINE PATTERN RVOTE.PDS REVISION B AUTHOR Your name COMPANY RYERSON DATE MM/DD/
CHIP RVOTE PAL16V CP NC NC A B C D NC NC GND ; Registered mode /OE NC NC NC NC NC TIE NO YES VCC
EQUATIONS ; The “: =” operator indicates a registered output. YES : = /ABCD + A/BCD + AB/CD + ABC/D + ABCD NO : = /A/B/C/D + /A/B/CD + /A/BC/D +/AB/C/D + A/B/C/D TIE : = /A/BCD + /AB/CD + /ABC/D + A/B/CD
SIMULATION TRACE_ON CP A B C D YES NO TIE SETF /CP OE ; Initialize clock & enable outputs (/OE=0) CLOCKF CP ; Applies 1 clock pulse to pin CP SETF A B C D ; 1 1 1 1 CLOCKF CP SETF /D ; 1 1 1 0 CLOCKF CP SETF /C ; 1 1 0 0 CLOCKF CP SETF /B ; 1 0 0 0 CLOCKF CP SETF /A ; 0 0 0 0 CLOCKF CP TRACE_OFF
A.8 Programming PLDs & EPROMs (ChipLab)
- All of the CHIPLAB functions are accessed from the main menu bar and the pull-down menus.
- It is recommended that the "mouse" has been used (for ease of operation) to access and select the items from the pull-down menus.
- Check the green light on the Chiplab programmer "pod" to confirm that power is being applied.
ChipLab's Main Screen (showing pull-down menus)
A.8.1 Program PLDS
Example devices: 1. AMD - PALCE16VH-25/
- Lattice - GAL16V8A
- PLACE FLOPPY DISK with prepared data file (PALASM - e.g. hex-7.jed) in disk drive (A or B). At the "DOS" prompt, type "Chiplab". Wait until the system initialization is complete.
- SELECT DEVICE: Access the "Device" pull-down menu. Sequence (with the mouse): a) Select b) Specify one of the following: AMD, CE16V8H-25/4, LDip 20 logic; or Lattice, 16V8A, LDip 20 logic. c) Select
- READ DATA FILE: Access the "File" pull-down menu. Sequence: a) Open b) Source file - e.g. "a:labl.jed" c) File format - JEDEC (Full), code 91 d) Read ... At this point, "File a:labl.jed loaded" should appear at the bottom of the screen.
File Data Device Config Options Help
Open… Ctrl+O Save as… Ctrl+S
DOS shell Exit
Fill RAM… Move data… Complement data…
Sumcheck data… Data editor… (^) Edit User data… Edit Jedec data…
Select…
Ctrl+D
Program Device…
Ctrl+P
Read device…
Ctrl+R
Verify device…
Ctrl+V
Select… Ctrl+D Program Device… Ctrl+P Read device… Ctrl+R Verify device… Ctrl+V Blank check only… Ctrl+D Illegal bit check only… Compare electronic ID only Erase EE device only Footnote…
General parameters… Memory parameters… Logic parameters…
Restore parameters… Save parameters…
Update Self-Test
System Log… Ctrl+E Set preferences
Help on help Keys for help Gen hlp ind F Mess hlp ind
About…
Footnote…
A.9 ChipWriter - Quick start tutorials
A.9.1 Tutorial 1: Programming an EPROM or Microcontroller from a master device
- Type CWEPROM
- Select the Device you are using as a master, using DEVICE/TYPE. Select the device type you are wishing to use and press . You will then be given a list of manufacturers who support the selected device type. Select the appropriate manufacturer and press . You will then be prompted for the device name. Choose the correct device name from the menu you are given and press to accept. The details of the device you have chosen will now be displayed at the bottom of the screen.
- Ensure that the data memory buffer size is large enough to hold the data to be read from the master device. You can change the buffer size using DATA/BUFFER-SIZE.
- Insert the master device in the programmer.
- Select PROCESS/READ to read the contents of the chip into the data memory buffer. Press to accept the default addresses.
- Select the device you are copying to, if it is different (see 2.).
- Now place the blank copy device in the programmer socket.
- Select PROCESS/PROGRAM. Press to accept the default addresses.
- The message: Device programmed and verified will be displayed.
A.9.2 Tutorial 2: Programming an EPROM or Microcontroller from a file on disk
- Type CWEPROM
- Select the Device you are using as a master, using DEVICE/TYPE. Select the device type you are wishing to use and press . You will then be given a list of manufacturers who support the selected device type. Select the appropriate manufacturer and press . You will then be prompted for the device name. Choose the correct device name from the menu you are given and press to accept. The details of the device you have chosen will now be displayed at the bottom of the screen.
- Ensure that the data memory buffer size is large enough to hold the data to be read from the master device. You can change the buffer size using DATA/BUFFER-SIZE.
- Select FILE/OPEN
- Specify the path and filename where your data is located.
- Select the file format used (HEX auto-recognition will detect any of the available HEX formats)
- Press to accept the default settings and load the data. A checksum will be displayed on the screen.
- Select the device you are copying to if it is different (see 2.)
- Place the blank device in the programmer socket.
- Select PROCESS/PROGRAM. Press to accept the default addresses.
- The message: Device programmed and verified will be displayed.
A.9.3 Tutorial 3: Programming a logic device from a file on disk
- Type CWPAL
- Select the device you are going to program using DEVICE/ MANUFACTURER. Select manufacturer and press . Choose the device name from the list on the screen by highlighting the correct device and pressing .
- Select FILE/OPEN.
- Specify the path and filename where your JEDEC file is located.
5. Press to accept the defaults. A checksum will be displayed once the file has loaded.
6. Place the blank device in the programmer socket.
- Select PROCESS/PROGRAM. The device will now be erased (where relevant), programmed, veri- fied and any test vectors present in the JEDEC file will be applied.
- The message: Device programmed and verified will be displayed.
Part B – MAX+PLUS II “Tutorial Introduction”
B.1 Objectives:
- The main objective of this lab is to know how to use MAX+PLUS II software. MAX+PLUS II is used for Synthesis of digital logic design using Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs). Note: See the Appendix B (course text), chapters B.1, B.2, and B.
B.2 Installing Your Own Copy of MAX+PLUS II – Done later
- System Requirements o IBM PC using Windows 95, 98 or NT (3.51 or 4.0) o CD drive for software installation o Available memory > 48 MB o Available Hard disk space > 80 MB
- Installation o Run the command <CD-ROM drive>:\pc\setup.exe . The setup program will guide you through the installation process. After installation you have to obtain the Li- cense File for "MAX+plus II 9.23 Baseline" from Altera (www.altera.com/maxplus2- student). When obtaining the License File you will be asked to provide the serial number of your hard disk. To obtain this number start MAX+plus II and click on the Options menu, License Setup and System Info. The hard disk serial number is then displayed. o The first time you start MAX+plus II it will ask you whether you want instructions to ob- tain a free license. Answer "No", and go to the web site to obtain your license file. o After you have provided to Altera the required information, the License File will be e- mailed to you along with instructions how to enable the software.
B.3 Procedure – Preparing Design Entry
Design entry can be performed by three different methods: using schematic capture, truth table, and writ- ing VHDL code. In this lab, we will use schematic capture and the truth table method to enter, compile, and simulate simple designs.
B.4 Pre-lab preparation
- To do the pre-lab you will need to logon to a department workstation in lab T
- To save your files, create the subdirectory max2work , [mkdir max2work]. Under the directory max2work create another directory called tutorial1. This will be working directory for the design cre- ated in this tutorial.
- Start up Max+plus II by typing max2win at the prompt. This will open Max+plus II window, which gives you access to an integrated suite of eleven application tools. Note: When Max+plus II starts for the first time, a file called maxplus2.ini will be created in your home directory. This is an initialization file required by Max+plus II and it takes a little time to cre- ate. Do not delete it! A directory called windows will also be created in your home directory. Do not delete it!
B.5 Creating a Schematic Design
Schematic designs are created with the Graphic Schematic Editor tool of Mux+plus II.
- To start Graphic Design Editor, select Max+plus II then Graphic Editor
- Refer to Appendix B.2 of the reference text and enter the schematic represented in Figure B.4 of Ap- pendix B.
- Save and check the design by selecting File then Project and then Save & Check. This will open the compiler. If there are no errors or warnings, proceed to the simulation.
B.6 Compiling and Simulating a Design
A design is simulated by compiling, creating input waveforms (test vectors), simulating and viewing the results.
- To open compiler select Max+plus II then Compiler
- Select Processing then Functional SNF Extractor and click Start in the compiler window. The output of the compilation is the simulator netlist file (.snf). The simulator also requires a simulator channel file (.scf) , which contains information about logic levels for input, output and hidden signals in the circuit. Each input and output is often referred to as a channel
- To create a simulator channel file, select Max+plus II then Waveform Editor. Refer to Appendix B.2.4 of reference text and select the channels for simulation
- Simulate the circuit by selecting Max+plus II then Simulator. Click start. Obtain printouts of the simulation and hand them in to your instructor.
B.7 Design Entry Using Truth Tables
In this section we will design a logic circuit using truth table. We will implement the truth table shown in Figure B.25 of Appendix B.4 (see reference text). It will be entered into the CAD system by drawing a timing diagram, which is equivalent to truth table.
- Open the Waveform Editor
- Specify the type of the file to be created by selecting File then Save As. In the box labeled File Name, type the name timing1.wdf.
- Specify the input and output signals (refer to Appendix B4.2 of the text book)
- Specify a waveform for the output of the circuit that corresponds to its truth table
- Select File then Save. Obtain printouts of the simulation and hand them in to your instructor
B.8 Mixed Design-Entry Methods
Here we will create a schematic that includes the circuit designed using the truth table in the pre-
vious section. Use the same directory as for the previous projects (see Appendix B5 of the reference
text)
- Open the Graphic Editor
- Specify the type of the file to be created by selecting File then Save As. In the box labeled File Name, type the name mixed1.gdf.
- Import the timing1 circuit into the Graphic Editor.
- Follow the procedure of Appendix B.5 of the reference text and draw the schematic of figure B.30. Save the schematic.
- Obtain printouts of the simulation and hand them in to your instructor
