Address Decoding - Microcomputer Structures - Lecture Slides, Slides of Microcomputers

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Address Decoding for Memory

and I/O

Address Decoding

• Address Decoding Designs
  • Full Address Decoding
  • Partial Address Decoding
  • Block Address Decoding
• Implementation
  • Random, Decoders, PROM, FPGA

The Memory Space

• 2 basic approaches
  • Memory mapped system – main memory and I/O space are just different addresses or regions – or memory mapped I/O (MMIO) - Addressing is the same pins for memory and I/O - Advantage – less pin and hardware complexity
  • Port Mapped I/O – have unique pins (signals) that differentiate memory and I/O address spaces - Advantage – If limited memory, memory is memory - Advantage – Large I/O space

Other architectures

• Harvard Architecture
  • Separate memory spaces for instructions and data
  • Requires pin(s) to differentiate
  • I/O is MMIO
• Check these out on www.wikipedia.com

Address Map

• When implementing a system the designer creates a memory map.
• Map would include where RAM, ROM and I/O are.

Full address decoding

• Each addressable location within the memory components responds to only a single unique address.

Ex continued

Partial Address Decoding

• Some of address lines are unused
• Least complex and most inexpensive
• Each component will actually respond to several addresses

Block Address decoding

• Compromise between full and partial.
• Don’t decode all of address lines but do decode more than the bare minimum.
• Less repeated addresses for each populated device

Designing the decode logic

• Multiple methods of implementing the decode logic
• One method is of course to implement it with “random logic” – i.e., AND gates, OR gates, inverters, NAND gates, NOR gates
• Advantage – speed
• Disadvantage – possibly the number of chips

Decoder Truth table

Example of decoder use

PROMS

• A PROM can also be use to implement logic functions
• Can use it to do address decoding

Example of PROM use

• Decoder design must be cheap and versitle.